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data sheet S6D1121 240 rgb source & 320 ltps with gram for 262k colors tft-lcd ve r. 1 . 0 0 system lsi division semiconductor business samsung electronics co., ltd. ( http://www.samsung.com/products/semiconductor/displaydriveric ) contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 2 contents 1. description ................................................................................................................. ........ 3 2. features .................................................................................................................... .......... 4 3. block diagram............................................................................................................... .... 5 3.1 pad configuration .......................................................................................................... ..............6 3.2 align key configuration and coordinate...........................................................................7 3.3 bump size .................................................................................................................. .........................9 3.4 pad center coordinates ..................................................................................................... .....10 4.display pin description ................................................................................................. 13 4.1 power su pply pi ns .......................................................................................................... ............13 4.2 host/external interface pins............................................................................................... .15 4.3 driver output pins ......................................................................................................... .............17 4.4 miscella neous pins......................................................................................................... ............18 4.5 interface pin configuration ................................................................................................ ..19 5. function al descri ption ............................................................................................... 20 5.1 system interface........................................................................................................... ..............20 5.2 interface specification.................................................................................................... ........27 5.3 ltps display timing generator .............................................................................................. 72 5.4 display function ........................................................................................................... ...............81 5.5 display data ram ........................................................................................................... ...............87 5.6 mtp (muti time programmable) ............................................................................................... 92 5.7 osc ........................................................................................................................ .............................95 5.8 power suppl y seque nce...................................................................................................... .....96 5.9 power circuit.............................................................................................................. ................101 5.10 gamma curve correction .................................................................................................... 103 6. r eset ....................................................................................................................... .......... 113 7. commands .................................................................................................................... .... 115 7.1 instruction table.......................................................................................................... ............115 7.2 instruction description .................................................................................................... ....118 8. dc / ac characteristics ............................................................................................. 167 8.1 absolute maximum ratings ................................................................................................... .167 8.2 lcd driver dc characterisics..............................................................................................1 68 8.3 cpu / rgb / serial interface ac characteristics..........................................................170 8.4 serial peripheral interface................................................................................................ .172 8.5 rgb interface.............................................................................................................. ................173 8.6 reset timing ............................................................................................................... ..................174 8.7 mddi io dc / ac characteristics ...........................................................................................1 75 8.8 sub panel signal characteristics .....................................................................................177 8.9 mtp dc / ac characteristics................................................................................................ ..179 9. applications ................................................................................................................ ... 180 9.1 appication circuit example ................................................................................................. ..180 revision history............................................................................................................... ................181 notice......................................................................................................................... ........... 183 free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 3 1. description S6D1121 is a single chip low power cmos lcd controller/driver for color ltps-tft-lcd displays of 320 gates and 240xrgb columns. it has a 1.38m-bit (240 x 18bit x 320) display ram and a full set of control functions. S6D1121 offers 10 kinds microprocessor interfaces: 8080-system (8-bit, 9-bit, 16-bit, 18bit), 6800-system (8-bit, 9-bit, 16-bit, 18bit), serial (3-pins) and vsync interface. it also supply 18-bit, 16-bit, 6-bit rgb interface for driving video signal directly from controller. the S6D1121 supports qualcomm?s high-speed serial interface, mddi (mobile display digital interface) type i, which is an implementation of client device video electronics standards association (vesa) standard. the mddi is a cost-effective low-power solution that enables high-speed short-range communication with a display device using a digital packet data link. the S6D1121 offers interface for sub panel driver ic which doesn?t support mddi: it can generate conventional mpu-interface protocol from mddi packet. the S6D1121 has various functions for reducing the power consumption of a lcd system: operating at low voltage (1.5v), register-controlled power-save mode, reduced the power consumption of backlight, partial display mode and so on. the ic has internal gram to store 240-rgb x 320 dot 262k-color image and an internal booster that generates the lcd driving voltage, breeder resistance and voltage follower circuit for lcd driver. this lsi is suitable for any medium-sized or small portable mobile solution requiring long-term driving capabilities, such as digital cellular phones supporting a web browser, bi-directional pagers, and small pdas. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 4 2. features z single chip ltps-tft-lcd controller/ driver with display ram. z display resolution: 240*rgb (h) *320(v) z display data ram (frame memory): 240 x 320 x 18-bit = 1,382,400bit z output - 240ch source outputs - common electrode output - ltps gate control output z display mode (color mode) - full color mode: 262k-colors - reduce color mode: 8-colors (3-bit binary mode) z display resolution - 240 x 320 display with 240 x 18-bit x 320 ram z mcu interface - vsync interface - 3-pin serial interface - 8-bit, 9-bit, 16-bit, 18-bit interface with 8080-series mcu - 8-bit, 9-bit, 16-bit, 18-bit interface with 6800-series mcu - 6-bit, 16-bit, 18-bit rgb interface with graphic controller z mddi (mobile display digital interface) support z sub panel driver ic control function support - conventional lcd driver ic (80 /68/stn -mode) can be selected as sub panel driver ic. z display features - partial display mode - writing to a window-ram address area by using a window-address function - software programmable color depth mode - line inversion for low cross talk z on chip - dc/dc converter - adjusted vcom generation - oscillator for display clock generation - timing generation non volatile memory z driving algorithm line inversion, frame inversion z apply voltage range - analog supply voltage range for vci to vss: 2.5v to 3.3v - i/o supply voltage range for vdd3 to vss3: 1.65v to 3.3v z output voltage levels - for the logic part:vdd to vss = 1.4 to 1.6 v (power supply for logic circuits) - for the source driver: avdd to avss = 3.4 to 6.0 v (power supply for driving circuits) gvdd to avss = 3.0 to 5.0 v (reference power supply for grayscale voltages) - for the gate driver: vgh to vgl = 13 to 27 v, vgh to vssc = +7.5 to +16.0 v, vgl to vssc = -11.0 to -5.5 v. - for the step up circuit: vci1 to vssc = 1.75 to 3.0 v (refer to instruction description) - for the ltps-lcd counter electrode: vcom amplitude (max) = 5.3v, vcomh to avss = 3.52 to 5.3v, vcoml to avss = 0.0 to 1.0v z lower power consumption, suitable for battery operated systems - cmos compatible inputs - optimized layout for cog assembly - operate temperature range: -40 to +85 free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 5 3. block diagram figure 3.1 S6D1121 block diagram free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 6 3.1 pad configuration table 3.1.1 S6D1121 pad dimensions size items pad name. x y unit chip size1) - 12320 1400 input pad 30 ?? 2 100 ?? 2 bumped pad size output pad 25 ?? 2 80 ?? 2 in wafer 15(typ.) 3 bumped pad height in chip under 2 um notes: 1. scribe line included in this chip size (scribe lane: 80um) 2. there is a kind of output bumped pads. the dimensions of bumped pads are 25umx80um. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 7 3.2 align key configuration and coordinate figure 3.2.1 cog and bump align key free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 8 c output b d a input figure 3.2.2 align key configuration notes: 1. gold bump height: 15 3 um (typical) 2. wafer thickness: 300um free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 9 3.3 bump size 3.3.1 bump pad array 30um 30um 5 um 5 um 25 um 7 um 155 um 7 um 100 um 80 um 80 um 20 um 20 um dummy dummy dummy 30 um dummy 30um 30um 5 um 5 um 25 um 7 um 155 um 7 um 100 um 80 um 80 um 20 um 20 um dummy dummy dummy 30 um dummy figure 3.3.1.1 bump pad information free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 10 3.4 pad center coordinates no pad name x y no pad name x y no pad name x y 1 dummy<1> -5950 -603 61 c12p -2950 -603 121 vdd3 50 -603 2 dummy<2> -5900 -603 62 c12m -2900 -603 122 vssc 100 -603 3 vcom -5850 -603 63 c12m -2850 -603 123 vssc 150 -603 4 vcom -5800 -603 64 c12m -2800 -603 124 vssc 200 -603 5 vcom -5750 -603 65 c11p -2750 -603 125 vssc 250 -603 6 vcom -5700 -603 66 c11p -2700 -603 126 vssc 300 -603 7 vcom -5650 -603 67 c11p -2650 -603 127 vssc 350 -603 8 vcom -5600 -603 68 c11p -2600 -603 128 avss 400 -603 9 vcom -5550 -603 69 c11p -2550 -603 129 avss 450 -603 10 resetb -5500 -603 70 c11m -2500 -603 130 avss 500 -603 11 c21p -5450 -603 71 c11m -2450 -603 131 avss 550 -603 12 c21p -5400 -603 72 c11m -2400 -603 132 avss 600 -603 13 c21p -5350 -603 73 c11m -2350 -603 133 avss 650 -603 14 c21m -5300 -603 74 c11m -2300 -603 134 vss3 700 -603 15 c21m -5250 -603 75 avdd -2250 -603 135 vss3 750 -603 16 c21m -5200 -603 76 avdd -2200 -603 136 vss3 800 -603 17 c22p -5150 -603 77 avdd -2150 -603 137 vss3 850 -603 18 c22p -5100 -603 78 avdd -2100 -603 138 vss3 900 -603 19 c22p -5050 -603 79 avdd -2050 -603 139 vss 950 -603 20 c22m -5000 -603 80 avdd -2000 -603 140 vss 1000 -603 21 c22m -4950 -603 81 vci_ref -1950 -603 141 vss 1050 -603 22 c22m -4900 -603 82 vci -1900 -603 142 vss 1100 -603 23 vgh -4850 -603 83 vci -1850 -603 143 vss 1150 -603 24 vgh -4800 -603 84 vci -1800 -603 144 vss 1200 -603 25 vgh -4750 -603 85 vci -1750 -603 145 ex_clk 1250 -603 26 vgh -4700 -603 86 vci -1700 -603 146 test_exclk_en 1300 -603 27 vgh -4650 -603 87 vci -1650 -603 147 im<3> 1350 -603 28 vgh -4600 -603 88 vci_mddi -1600 -603 148 im<2> 1400 -603 29 dummy<3> -4550 -603 89 vci_mddi -1550 -603 149 im<1> 1450 -603 30 vglrout -4500 -603 90 vci_mddi -1500 -603 150 im<0> 1500 -603 31 vglrout -4450 -603 91 vci_mddi -1450 -603 151 resetb 1550 -603 32 vglrout -4400 -603 92 mdp -1400 -603 152 pregb 1600 -603 33 vglrout -4350 -603 93 mdp -1350 -603 153 db<17> 1650 -603 34 vglrout -4300 -603 94 mdn -1300 -603 154 db<16> 1700 -603 35 vglrout -4250 -603 95 mdn -1250 -603 155 db<15> 1750 -603 36 vgl -4200 -603 96 msp -1200 -603 156 db<14> 1800 -603 37 vgl -4150 -603 97 msp -1150 -603 157 db<13> 1850 -603 38 vgl -4100 -603 98 msn -1100 -603 158 db<12> 1900 -603 39 vgl -4050 -603 99 msn -1050 -603 159 db<11> 1950 -603 40 vgl -4000 -603 100 vss_mddi -1000 -603 160 db<10> 2000 -603 41 vgl -3950 -603 101 vss_mddi -950 -603 161 db<9> 2050 -603 42 dummy<4> -3900 -603 102 vss_mddi -900 -603 162 db<8> 2100 -603 43 dummy<5> -3850 -603 103 vss_mddi -850 -603 163 db<7> 2150 -603 44 vr1 -3800 -603 104 dummy<6> -800 -603 164 db<6> 2200 -603 45 vr1 -3750 -603 105 vgs -750 -603 165 db<5> 2250 -603 46 vr1 -3700 -603 106 vgs -700 -603 166 db<4> 2300 -603 47 vr1 -3650 -603 107 vdd -650 -603 167 db<3> 2350 -603 48 vr1 -3600 -603 108 vdd -600 -603 168 db<2> 2400 -603 49 vr2 -3550 -603 109 vdd -550 -603 169 db<1> 2450 -603 50 vr2 -3500 -603 110 vdd -500 -603 170 db<0> 2500 -603 51 vr2 -3450 -603 111 vdd -450 -603 171 e_rdb 2550 -603 52 vr2 -3400 -603 112 vdd -400 -603 172 rw_wrb 2600 -603 53 vr2 -3350 -603 113 vdd -350 -603 173 rs 2650 -603 54 vci1 -3300 -603 114 vdd -300 -603 174 csb 2700 -603 55 vci1 -3250 -603 115 vdd -250 -603 175 vsync 2750 -603 56 vci1 -3200 -603 116 vdd -200 -603 176 hsync 2800 -603 57 vci1 -3150 -603 117 vdd3 -150 -603 177 dotclk 2850 -603 58 vci1 -3100 -603 118 vdd3 -100 -603 178 enable 2900 -603 59 c12p -3050 -603 119 vdd3 -50 -603 179 pd<17> 2950 -603 60 c12p -3000 -603 120 vdd3 0 -603 180 pd<16> 3000 -603 free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 11 no pad name x y no pad name x y no pad name x y 181 pd<15> 3050 -603 241 dummy<10> 5827.5 613 301 s<190> 3127.5 613 182 pd<14> 3100 -603 242 r_gspb 5782.5 613 302 s<189> 3082.5 613 183 pd<13> 3150 -603 243 r_gclk1b 5737.5 613 303 s<188> 3037.5 613 184 pd<12> 3200 -603 244 r_gclk2b 5692.5 613 304 s<187> 2992.5 613 185 pd<11> 3250 -603 245 r_gclk3b 5647.5 613 305 s<186> 2947.5 613 186 pd<10> 3300 -603 246 r_gclk4b 5602.5 613 306 s<185> 2902.5 613 187 pd<9> 3350 -603 247 dummy<12> 5557.5 613 307 s<184> 2857.5 613 188 pd<8> 3400 -603 248 dummy<13> 5512.5 613 308 s<183> 2812.5 613 189 pd<7> 3450 -603 249 dummy<14> 5467.5 613 309 s<182> 2767.5 613 190 pd<6> 3500 -603 250 s<241> 5422.5 613 310 s<181> 2722.5 613 191 pd<5> 3550 -603 251 s<240> 5377.5 613 311 s<180> 2677.5 613 192 pd<4> 3600 -603 252 s<239> 5332.5 613 312 s<179> 2632.5 613 193 pd<3> 3650 -603 253 s<238> 5287.5 613 313 s<178> 2587.5 613 194 pd<2> 3700 -603 254 s<237> 5242.5 613 314 s<177> 2542.5 613 195 pd<1> 3750 -603 255 s<236> 5197.5 613 315 s<176> 2497.5 613 196 pd<0> 3800 -603 256 s<235> 5152.5 613 316 s<175> 2452.5 613 197 test_mode<2> 3850 -603 257 s<234> 5107.5 613 317 s<174> 2407.5 6 13 198 test_mode<1> 3900 -603 258 s<233> 5062.5 613 318 s<173> 2362.5 6 13 199 test_mode<0> 3950 -603 259 s<232> 5017.5 613 319 s<172> 2317.5 6 13 200 disptmg 4000 -603 260 s<231> 4972.5 613 320 s<171> 2272.5 613 201 prec 4050 -603 261 s<230> 4927.5 613 321 s<170> 2227.5 613 202 eq 4100 -603 262 s<229> 4882.5 613 322 s<169> 2182.5 613 203 m 4150 -603 263 s<228> 4837.5 613 323 s<168> 2137.5 613 204 flm 4200 -603 264 s<227> 4792.5 613 324 s<167> 2092.5 613 205 cl1 4250 -603 265 s<226> 4747.5 613 325 s<166> 2047.5 613 206 tso<1> 4300 -603 266 s<225> 4702.5 613 326 s<165> 2002.5 613 207 tso<0> 4350 -603 267 s<224> 4657.5 613 327 s<164> 1957.5 613 208 dummy<7> 4400 -603 268 s<223> 4612.5 613 328 s<163> 1912.5 613 209 mtp_pp 4450 -603 269 s<222> 4567.5 613 329 s<162> 1867.5 613 210 mtp_ep 4500 -603 270 s<221> 4522.5 613 330 s<161> 1822.5 613 211 vcoml 4550 -603 271 s<220> 4477.5 613 331 s<160> 1777.5 613 212 vcoml 4600 -603 272 s<219> 4432.5 613 332 s<159> 1732.5 613 213 vcoml 4650 -603 273 s<218> 4387.5 613 333 s<158> 1687.5 613 214 vcomh 4700 -603 274 s<217> 4342.5 613 334 s<157> 1642.5 613 215 vcomh 4750 -603 275 s<216> 4297.5 613 335 s<156> 1597.5 613 216 vcomh 4800 -603 276 s<215> 4252.5 613 336 s<155> 1552.5 613 217 vcomr 4850 -603 277 s<214> 4207.5 613 337 s<154> 1507.5 613 218 gvdd 4900 -603 278 s<213> 4162.5 613 338 s<153> 1462.5 613 219 gvdd 4950 -603 279 s<212> 4117.5 613 339 s<152> 1417.5 613 220 vcom_prec 5000 -603 280 s<211> 4072.5 613 340 s<151> 1372.5 613 221 vcom_prec 5050 -603 281 s<210> 4027.5 613 341 s<150> 1327.5 613 222 vcom_prec 5100 -603 282 s<209> 3982.5 613 342 s<149> 1282.5 613 223 vcom_dc 5150 -603 283 s<208> 3937.5 613 343 s<148> 1237.5 613 224 vcom_dc 5200 -603 284 s<207> 3892.5 613 344 s<147> 1192.5 613 225 vcom_dc 5250 -603 285 s<206> 3847.5 613 345 s<146> 1147.5 613 226 vrefi 5300 -603 286 s<205> 3802.5 613 346 s<145> 1102.5 613 227 vrefo 5350 -603 287 s<204> 3757.5 613 347 s<144> 1057.5 613 228 resetb 5400 -603 288 s<203> 3712.5 613 348 s<143> 1012.5 613 229 contact_vss3 5450 -603 289 s<202> 3667.5 613 349 s<142> 967.5 6 13 230 contact_vss3 5500 -603 290 s<201> 3622.5 613 350 s<141> 922.5 6 13 231 vcom 5550 -603 291 s<200> 3577.5 613 351 s<140> 877.5 613 232 vcom 5600 -603 292 s<199> 3532.5 613 352 s<139> 832.5 613 233 vcom 5650 -603 293 s<198> 3487.5 613 353 s<138> 787.5 613 234 vcom 5700 -603 294 s<197> 3442.5 613 354 s<137> 742.5 613 235 vcom 5750 -603 295 s<196> 3397.5 613 355 s<136> 697.5 613 236 vcom 5800 -603 296 s<195> 3352.5 613 356 s<135> 652.5 613 237 vcom 5850 -603 297 s<194> 3307.5 613 357 s<134> 607.5 613 238 dummy<8> 5900 -603 298 s<193> 3262.5 613 358 s<133> 562.5 613 239 dummy<9> 5950 -603 299 s<192> 3217.5 613 359 s<132> 517.5 613 240 dummy<11> 5872.5 613 300 s<191> 3172.5 613 360 s<131> 472.5 613 free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 12 no pad name x y no pad name x y no pad name x y 361 s<130> 427.5 613 411 s<80> -1822.5 613 461 s<30> -4072.5 613 362 s<129> 382.5 613 412 s<79> -1867.5 613 462 s<29> -4117.5 613 363 s<128> 337.5 613 413 s<78> -1912.5 613 463 s<28> -4162.5 613 364 s<127> 292.5 613 414 s<77> -1957.5 613 464 s<27> -4207.5 613 365 s<126> 247.5 613 415 s<76> -2002.5 613 465 s<26> -4252.5 613 366 s<125> 202.5 613 416 s<75> -2047.5 613 466 s<25> -4297.5 613 367 s<124> 157.5 613 417 s<74> -2092.5 613 467 s<24> -4342.5 613 368 s<123> 112.5 613 418 s<73> -2137.5 613 468 s<23> -4387.5 613 369 s<122> 67.5 613 419 s<72> -2182.5 613 469 s<22> -4432.5 613 370 s<121> 22.5 613 420 s<71> -2227.5 613 470 s<21> -4477.5 613 371 s<120> -22.5 613 421 s<70> -2272.5 613 471 s<20> -4522.5 613 372 s<119> -67.5 613 422 s<69> -2317.5 613 472 s<19> -4567.5 613 373 s<118> -112.5 613 423 s<68> -2362.5 613 473 s<18> -4612.5 613 374 s<117> -157.5 613 424 s<67> -2407.5 613 474 s<17> -4657.5 613 375 s<116> -202.5 613 425 s<66> -2452.5 613 475 s<16> -4702.5 613 376 s<115> -247.5 613 426 s<65> -2497.5 613 476 s<15> -4747.5 613 377 s<114> -292.5 613 427 s<64> -2542.5 613 477 s<14> -4792.5 613 378 s<113> -337.5 613 428 s<63> -2587.5 613 478 s<13> -4837.5 613 379 s<112> -382.5 613 429 s<62> -2632.5 613 479 s<12> -4882.5 613 380 s<111> -427.5 613 430 s<61> -2677.5 613 480 s<11> -4927.5 613 381 s<110> -472.5 613 431 s<60> -2722.5 613 481 s<10> -4972.5 613 382 s<109> -517.5 613 432 s<59> -2767.5 613 482 s<9> -5017.5 613 383 s<108> -562.5 613 433 s<58> -2812.5 613 483 s<8> -5062.5 613 384 s<107> -607.5 613 434 s<57> -2857.5 613 484 s<7> -5107.5 613 385 s<106> -652.5 613 435 s<56> -2902.5 613 485 s<6> -5152.5 613 386 s<105> -697.5 613 436 s<55> -2947.5 613 486 s<5> -5197.5 613 387 s<104> -742.5 613 437 s<54> -2992.5 613 487 s<4> -5242.5 613 388 s<103> -787.5 613 438 s<53> -3037.5 613 488 s<3> -5287.5 613 389 s<102> -832.5 613 439 s<52> -3082.5 613 489 s<2> -5332.5 613 390 s<101> -877.5 613 440 s<51> -3127.5 613 490 s<1> -5377.5 613 391 s<100> -922.5 613 441 s<50> -3172.5 613 491 s<0> -5422.5 613 392 s<99> -967.5 613 442 s<49> -3217.5 613 492 rswb -5467.5 613 393 s<98> -1012.5 613 443 s<48> -3262.5 613 493 gswb -5512.5 613 394 s<97> -1057.5 613 444 s<47> -3307.5 613 494 bswb -5557.5 613 395 s<96> -1102.5 613 445 s<46> -3352.5 613 495 l_gclk4b -5602.5 613 396 s<95> -1147.5 613 446 s<45> -3397.5 613 496 l_gclk3b -5647.5 613 397 s<94> -1192.5 613 447 s<44> -3442.5 613 497 l_gclk2b -5692.5 613 398 s<93> -1237.5 613 448 s<43> -3487.5 613 498 l_gclk1b -5737.5 613 399 s<92> -1282.5 613 449 s<42> -3532.5 613 499 l_gspb -5782.5 613 400 s<91> -1327.5 613 450 s<41> -3577.5 613 500 dummy<15> -5827.5 61 3 401 s<90> -1372.5 613 451 s<40> -3622.5 613 501 dummy<16> -5872.5 61 3 402 s<89> -1417.5 613 452 s<39> -3667.5 613 403 s<88> -1462.5 613 453 s<38> -3712.5 613 404 s<87> -1507.5 613 454 s<37> -3757.5 613 405 s<86> -1552.5 613 455 s<36> -3802.5 613 406 s<85> -1597.5 613 456 s<35> -3847.5 613 407 s<84> -1642.5 613 457 s<34> -3892.5 613 408 s<83> -1687.5 613 458 s<33> -3937.5 613 409 s<82> -1732.5 613 459 s<32> -3982.5 613 410 s<81> -1777.5 613 460 s<31> -4027.5 613 free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 13 4.display pin description 4.1 power supply pins table 4.1.1 power supply pins symbol i/o description vdd3 i power i/o power supply for external interface. (vdd3: +1.65 ~ +3.3 v) avdd o power a power output pin for source driver block that is generated from power block. connect a capacitor for stabilization. (avdd: +3.4 ~ +6.0 v) gvdd o power a standard level for grayscale voltage generator. connect a capacitor for stabilization. when internal gvdd generator is not used, connect an external power supply. (gvdd = 3.0 ~ 5.0v & avdd ? 0.5 v) vci i power analog power supply (vci : 2.5 ~ 3.3v) vci_ref i power a reference voltage for vci. must connect to vci at fpc vci_mddi i power analog power supply (vci_mddi : 2.5 ~ 3.3v) vss i power system ground. (0v) vss3 i power system ground level for i/o. vss_mddi i power system ground level for mddi block vssc i power system ground level for step up circuit block. mtp_ep i power power supply for non-volatile memory. (21.5 0.5v) if mtp is not used, this pad should be floated. mtp_pp i power power supply for non-volatile memory (17.5 0.5v) if mtp is not used, this pad should be floated. avss i power system ground level for source driver block. vgs i power gamma ground level. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 14 table 4.1.2 power supply pins (continued) symbol i/o description vci1 o power a reference voltage in step-up circuit 1. connect a capacitor for stabilization. vci1 can not exceed 3 v. vrefo o a reference voltage for gvdd, vcomh, vcoml. (external short to vrefi) vrefi i a reference voltage for gvdd, vcomh, vcoml. vcomprec o when the coupling mode is driven, this pin is used. connect to vcom. vcom o outputs the square wave signal obtained through common modulation of vp-p. - r16h : coma is low, vcom = vcomh ? avss - r16h : coma is high, vcom = vcomh ? vcoml vcomdc o when the coupling mode is driven, this pin is used for the common center voltage. vcomr i/o a reference voltage of vcomh. when vcomh is externally adjusted, halt the internal adjuster of vcomh by setting the register and inserting a variable resistor between gvdd and vss. w hen this pin is not externally adjusted, leave it open and adjust vcomh by setting the internal register. vcomh o this pin indicates a high level of vcom that is generated from driving the vcom alternation. connect this pin to the capacitor for stabilization. vcoml o when the vcom alternation is driven, this pin indicates a low level of vcom. an internal register can be used to adjust the voltage. connect this pin to a capacitor for stabilization, and be careful of the polarity of capacitor for available voltage. (0 ~ 1.0v) vgh o power this pin is a positive power output pin for gate driver, internal step-up circuits, bias circuits, and operational amplifiers. connect a capacitor for stabilization. range : 7.5 v ~ 16.0 v. external cap. 2.2uf. vgl o power vgl is vglrout regulator power voltage. to protect ic against latch up, connect the cathode of the schottky diode to the vss pad. and the anode of the schottky diode to the vgl pad. refer to the application circuit. connect a capacitor for stabilization. range : -11.0v ~ -5.5v. external cap. 1.0uf. vglrout o power vglrout voltage is gate negative voltage. vglrout is generated by regulator amp. vglrc register is vglrout level control. range : -10.5v ~ -5.0v vr1 o power vr1 voltage is vgh, vgl reference voltage range : 2.0v ~ 5.0v vr2 o power vr2 voltage is vgh reference voltage range : 2.0v ~ 5.0v ex_clk i/o in input mode, it will be used as test pin [581khz ~ 1730khz frequency] in output mode, leave this pin open. used to analyze the internal oscillation frequency. c11m,c11p c12m,c12p - connect the step-up capacitor for generating the avdd level. c12m & c12p can be used as an option only for high current consumption. c21m,c21p c22m,c22p - connect a step-up capacitor for generating the vgh, vgl level. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 15 4.2 host/external interface pins table 4.2.1 host interface pins symbol i/o description im[3:0] i system interface selection pins. csb i chip selection pin, active low. rs i data / command selection pin. when parallel data transfer has been selected, this pin is used to distinguish between data from memory and commands. low: indicates that data (db bus) is commands, high: indicates that data (db bus) is display data. rw_wrb i 68-system i/f: read/write select signal low(write), high(read) 80-system i/f: write strobe signal. active low. selecting rgb mode, it is used as scl. e_rdb i 68-system i/f: strobe signal. active high. 80-system i/f: read strobe signal. active low selecting rgb mode, it is used as sdi. db[17:0] i/o data bus pins. unused pins are fixed to vss3. resetb i external reset pin. active low. initializes the ic, when this signal is low. must be reset after the power is stable. note: these three pins are connected together inside the chip. so when one is used as a reset pin, the other one should be left floating . enable i data enable pin in rgb i/f mode. if not used, please fix this pin at vss3 level. vsync i vertical synchronous pin in rgb i/f mode. if not used, please fix this pin at vss3 level. hsync i horizontal synchronous pin in rgb i/f mode. if not used, please fix this pin at vss3 level. dotclk i data clock pin in rgb i/f mode. if not used, please fix this pin at vss3 level. pd[17:0] i/o rgb data input bus. 18-bit interface: pd 17-0 16-bit interface: pd 17-13, pd 11-1 6-bit interface: pd 17-12 in the mddi mode, these pins are used for data bus of sub panel driver ic. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 16 table 4.2.2 mddi interface pins symbol i/o description mdp i/o positive mddi data pin. if mddi is not used, this pad should be floating. mdn i/o negative mddi data pin. if mddi is not used, this pad should be floating. msp i positive mddi strobe pin. if mddi is not used, this pad should be floating. msn i negative mddi strobe pin. if mddi is not used, this pad should be floating. db[17:13] (not used) o in mddi mode, these pins should be floating. gpio[9:0] (db[12:3]) i/o general purpose input/output pins. if gpio is not used in mddi mode, this pin should be fixed to vss3. s_csb (db[2]) o chip select for sub panel driver ic. low: sub panel driver ic is selected and can be accessed. high: sub panel driver ic is not selected and can not be accessed. if sub panel is not used in mddi mode, this pin should be floating s_rs (db[1]) o register select for sub panel driver ic. low : index/status, high : control must be fixed at vss level, when this signal is not used. if sub panel is not used in mddi mode, this pin should be floating s_wrb (db[0]) o write strobe signal for sub panel driver ic. only 80-system 18/16 bit mode is enabled, so data is fetched at the rising edge. if sub panel is not used in mddi mode, this pin should be floating s_db17-0 (pd[17:0]) o for sub panel, this pin can be used to transfer db [17:0] data to sub panel driver ic. if sub panel is not used in mddi mode, this pin should be floating. hsync vsync enable dotclk i in mddi mode, fixed it to vss3. rw_wrb e_rdb rs i in mddi mode, fixed it to vss3. csb i in mddi mode, fixed it to vdd3. note : in mddi mode, mdp(msp), mdn(msn) ports should be terminated with 100 ? resister free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 17 4.3 driver output pins table 4.3.1 source output pins symbol i/o description s1 to s240 o source driver output pins. table 4.3.2 gate driver control pins symbol i/o description lgspb o stb output (even: left side). this pin is a gate start pulse signal. amplitude: vgh-vglrout lgclk1b o clk 1 output (even: left side). this pin is a gate clock signal. amplitude: vgh-vglrout lgclk2b o clk 2 output (even: left side). this pin is a gate clock signal. amplitude: vgh-vglrout lgclk3b o clk 3 output (even: left side). this pin is a gate clock signal. amplitude: vgh-vglrout lgclk4b o clk 4 output (even: left side). this pin is a gate clock signal. amplitude: vgh-vglrout rgspb o stb output (odd: right side). this pin is a gate start pulse signal. amplitude: vgh-vglrout rgclk1b o clk 1 output (odd: right side). this pin is a gate clock signal. amplitude: vgh-vglrout rgclk2b o clk 2 output (odd: right side). this pin is a gate clock signal. amplitude: vgh-vglrout rgclk3b o clk 3 output (odd: right side). this pin is a gate clock signal. amplitude: vgh-vglrout rgclk4b o clk 4 output (odd: right side). this pin is a gate clock signal. amplitude: vgh-vglrout table 4.3.3 rgb switch control pins symbol i/o description rswb o this pin is panel of multi-plectra control signal. select signal. signal is outputted to the timing set as r72h and r75h. amplitude: vgh-vglrout gswb o this pin is panel of multi-plectra control signal. select signal. signal is outputted to the timing set as r73h and r76h. amplitude: vgh-vglrout bswb o this pin is panel of multi-plectra control signal. select signal. signal is outputted to the timing set as r74h and r7h7. amplitude: vgh-vglrout free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 18 4.4 miscellaneous pins table 4.4.1 miscellaneous pins symbol i/o description test_mode0 test_mode2 i input pins for test. in normal operation, connect this pin to vss3. test_mode1 i input pin for test. in normal opera tion, connect this pin to vss3 in rgb i/o sharing mode, this pin should be fixed to vdd3. disptmg/m/ cl1/flm/ tso1/ tso0 /prec/eq o output pins for test. in normal operation, leave this pin open. dummy - dummy pin. open or connect vss3. s0, s241 o source driver output pins. (s0 = s1, s241 = 240) free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 19 4.5 interface pin configuration table 4.5.1 source output pins 68 system 80 system rgb (*note1) mddi mode pin name 18bit 16bit 9bit 8bit 18bit 16bit 9bit 8bit normal i/o sharing mddi im[0] 0 0 1 1 0 0 1 1 id id 0 im[1] 0 0 0 0 1 1 1 1 0 0 0 im[2] 0 0 0 0 0 0 0 0 1 1 1 im[3] 1 0 1 0 1 0 1 0 0 0 1 mdp floating floating floating floating floating floating floating floating floating floating mdp mdn floating floating floating floating floating floating floating floating floating floating mdn msp floating floating floating floating floating floating floating floating floating floating msp msn floating floating floating floating floating floating floating floating floating floating msn db[17:13] db[17:13] db[17:13] db[17:13] db[17:13] db[17:13] db[17:13] db[17:13] db[17:13] vss3 pd[17:13] floating db[12:10] db[12:10] db[12:10] db[12:10] db[12:10] db[12:10] db[12:10] db[12:10] db[12:10] vss3 pd[12:10] gpio[9:7] db[9] db[9] floating db[9] floating db[9] floating db[9] floating vss3 pd[9] gpio[6] db[8:3] db[8:3] db[8:3] floating floating db[8:3] db[8:1] floating floating vss3 pd[8:3] gpio[5:0] db[2] db[2] db[2] floating floating db[2] db[2] floating floating vss3 pd[2] s_csb db[1] db[1] db[1] floating floating db[1] db[1] floating floating vss3 pd[1] s_rs db[0] db[0] floating floating floating db[0] vdd3 floating floating vss3 pd[0] s_wrb pd[17:0] floating floating floating floating floating floating floating floating pd[17:0] floating s_db(*note2) csb csb csb csb csb csb csb csb csb csb csb vdd3 rw_wrb rw rw rw rw wrb wrb wrb wrb scl scl vss3 e_rdb e e e e rdb rdb rdb rdb sdi sdi vss3 rs rs rs rs rs rs rs rs rs vss3 vss3 vss3 vsync vss3 vss3 vss3 vss3 vss3 vss3 vss3 vss3 vsync vsync vss3 hsync vss3 vss3 vss3 vss3 vss3 vss3 vss3 vss3 hsync hsync vss3 dotclk vss3 vss3 vss3 vss3 vss3 vss3 vss3 vss3 dotclk dotclk vss3 enable vss3 vss3 vss3 vss3 vss3 vss3 vss3 vss3 enable enable vss3 test_mode[2] 0 0 0 0 0 0 0 0 0 0 0 test_mode[1] 0 0 0 0 0 0 0 0 0 1 0 test_mode[0] 0 0 0 0 0 0 0 0 0 0 0 tso[0] floating floating floating floating floating floating floating floating sdo sdo floating prec floating floating floating floating floating floating floating floating floating floating floating eq floating floating floating floating floating floating floating floating floating floating floating m floating floating floating floating floating floating floating floating floating floating floating [notes] interface description remark rgb 18bit i/f : pd[17:0] 16bit i/f : pd[17:13], pd[11:1] 6bit i/f : pd[17:12] unused pins are not fixed any value, because of floating state which is defined output pins mddi pd[17:0] : s_db[17:0] pd [17:0] is defined as output. these pins are for sub panel ddi control signals for details, see ?sub panel ddi control? section. using for rgb i/o sharing mode, test_mode [2:0] must be fixed to ?3?b010? all unused input pins except for mddi ldvs and csb pins must be fixed to vss3. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 20 5. functional description 5.1 system interface S6D1121 has twelve high-speed system interfaces: 80-system 18/16/9/8bit cpu interfaces, 68-system 18/16/9/8bit cpu interfaces, two external display interface (rgb interface, vsync interface), and two serial interfaces (spi: serial peripheral interface, mddi: high speed serial interface). the im [3:0] pins determine the interface mode. 5.1.1 interface type selection the selection of a given interfaces are done by setting im [3:0] pins as show in table 5.1.1.1. table 5.1.1.1 system interface type selection and db pins assignment im3 im2 im1 im0/id mpu interface mode db pin assign vss vss vss vss 68-system 16-bit bus interface db17-10, db8-1 vss vss vss vdd3 68-system 8-bit bus interface db17-10 vss vss vdd3 vss 80-system 16-bit bus interface db17-10, db8-1 vss vss vdd3 vdd3 80-system 8-bit bus interface db17-10 vss vdd3 vss id serial peripheral interface (spi) e_rdb,tso[0] (sdi, sdo) vss vdd3 vdd3 * non-selecting - vdd3 vss vss vss 68-system 18-bit bus interface db17-0 vdd3 vss vss vdd3 68-system 9-bit bus interface db17-9 vdd3 vss vdd3 vss 80-system 18-bit bus interface db17-0 vdd3 vss vdd3 vdd3 80-system 9-bit bus interface db17-9 vdd3 vdd3 vss * mddi interface - when a spi mode is selected, the im0 pin is used as id setting bit for a device code. the other cases above, setting prohibited . by setting the test_mode pins, pd bus can reduce as shown in table 5.1.1.2. table 5.1.1.2 rgb interface type selection and db/pd pins assignment test_mode[2:0] rgb interface mode db pin assign 18-bit parallel bus interface db17-0 16-bit parallel bus interface db17-13, db11-1 vss vdd3 vss 6-bit parallel bus interface db17-12 18-bit parallel bus interface pd17-0 16-bit parallel bus interface pd17-13, pd11-1 vss vss vss 6-bit parallel bus interface pd17-12 in case of the i/o sharing db bus and pd bus, the test_mode pins must be fixed to ?010?. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 21 5.1.2 register type selection the S6D1121 has three 18-bit registers: an index register (ir), a write data register (wdr), and a read data register (rdr). th e ir is a register to store index information from each control r egister. the wdr is a register that temporarily stores data to b e written into each control register and gram. the rdr is a register to temporarily store data which is read from the gram. the data to be written to gram from mpu is once written to the wdr and then automatically written to gram by internal operation. since the data is read from gram through the rdr, the data read out first is invalid and the data following that is read out normally. table 5.1.2.1 register selection (18-/16-/9-/8- parallel interface) system rw_wrb e_rdb rs operations 0 1 0 write index to ir 1 1 0 read internal status (current gate line status) 0 1 1 write to control register and gram through wdr 68 1 1 1 read from gram and control register through rdr 0 1 0 write index to ir 1 0 0 read internal status (current gate line status) 0 1 1 write to control register and gram through wdr 80 1 0 1 read from gram and control register through rdr table 5.1.2.2 register selection (serial peripheral interface) r/w bit rs bit operations 0 0 write index to ir 1 0 read internal status 0 1 write data to control register and gram through wdr 1 1 read data from gram and control register through rdr free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 22 5.1.3 data transfer mode selection when the 18-bit parallel interface is selected, the length of 1 pixel is fixed to 18 bits. with the 16-bit, 9-bit or 8-bit para llel interface, however, the length of 1 pixel can be selected from 18 or 16 bits. if the 16-bit, 9-bit or 8-bit parallel interface is selected, therefore, several modes of transferring data to the display ram are selectable. the mode is selected by using the tri, dfm registers. table 5.1.3.1 interface and data transfer mode tri dfm interface number of data of 1 pixel mode of transferring 1-pixel data 0 0 68/80-system 18bit 18-bit 18-bit transfer 0 0 68/80-system 16bit 16-bit 16-bit transfer 0 0 68/80-system 9bit 18-bit 9-bit transfer twice 0 0 68/80-system 8bit 16-bit 8-bit transfer twice 1 0 80-system 16bit 18-bit 16-bit + 2-bit transfer 1 1 80-system 16bit 18-bit 2-bit + 16-bit transfer 1 0 80-system 8bit 18-bit 6bit transfer three times 1 1 80-system 8bit 16-bit 6bit transfer three times x x 18-bit 18-bit 18-bit transfer x x 16-bit 16-bit 16-bit transfer x x rgb 6-bit 18-bit 6-bit transfer three times remark x: don?t care (h/l) 5.1.3.1 68/80 system data transfer mode selection db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 input data r5 r4 r3 r2 r1 r0 *s (3n + 1) / **s (720 - 3n) g5 g4 g3 g2 g1 g0 *s (3n + 2) / **s (719 - 3n) b5 b4 b3 b2 b1 b0 *s (3n + 3) / **s(718 - 3n) rgb arrangement output note: n= lower 8 bits of address (0 to 239) and *(a series in case of ss= ? 0") / ** (a series in case of ss= ? 1") figure 5.1.3.1.1 68/80-system 18-bit interface (tri=0, dfm=0) db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 input data r5 r4 r3 r2 r1 r0 s (3n + 1) g5 g4 g3 g2 g1 g0 s (3n + 2) b5 b4 b3 b2 b1 b0 s (3n + 3) rgb arrangement output note: n= lower 8 bits of address (0 to 239) figure 5.1.3.1.2 68/80-system 16-bit interface (tri=0, dfm=0) free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 23 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 input data r5 r4 r3 r2 r1 r0 s (3n + 1) g5 g4 g3 g2 g1 g0 s (3n + 2) b5 b4 b3 b2 b1 b0 s (3n + 3) rgb arrangement output note: n= lower 8 bits of address (0 to 239) 1st transmission db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 2nd transmission figure 5.1.3.1.3 68/80-system 9-bit interface (tri=0, dfm=0) db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 input data r5 r4 r3 r2 r1 r0 s (3n + 1) g5 g4 g3 g2 g1 g0 s (3n + 2) b5 b4 b3 b2 b1 b0 s (3n + 3) rgb arrangement output note: n= lower 8 bits of address (0 to 239) 1st transmission 2nd transmission figure 5.1.3.1.4 68/80-system 8-bit interface (tri=0, dfm=0) db 17 db 16 db 15 db 14 db 13 db 12 input data r5 r4 r3 r2 r1 r0 s (3n+1) g5 g4 g3 g2 g1 g0 s (3n+2) b5 b4 b3 b2 b1 b0 s (3n+3) rgb arrangement output note: n= lower 8 bits of address (0 to 239) 1st transmission 2nd transmissio n db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 17 db 16 figure 5.1.3.1.5 80-system 16-bit interface (tri=1, dfm=0): 2 times transmission (262 k color) db 2 db 1 db 17 db 16 db 15 db 14 input data r5 r4 r3 r2 r1 r0 s (3n+1) g5 g4 g3 g2 g1 g0 s (3n+2) b5 b4 b3 b2 b1 b0 s (3n+3) rgb arrangement output note: n= lower 8 bits of address (0 to 239) 1st transmissio n 2nd transmission db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 figure 5.1.3.1.6 80-system 16-bit interface (tri=1, dfm=1): 2 times transmission (262 k color) free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 24 db 17 db 16 db 15 db 14 db 13 db 12 input data r5 r4 r3 r2 r1 r0 s (3n + 1) g5 g4 g3 g2 g1 g0 s (3n + 2) b5 b4 b3 b2 b1 b0 s (3n + 3) rgb arrangement output note: n= lower 8 bits of address (0 to 239) 1st transmission 2nd transmission 3rd transmission db 17 db 16 db 15 db 14 db 13 db 12 db 17 db 16 db 15 db 14 db 13 db 12 figure 5.1.3.1.7 80-system 8-bit interface (tri=1, dfm=0): 3 times transmission (262 k color) db 17 db 16 db 15 db 14 db 13 db 12 input data r5 r4 r3 r2 r1 r0 s (3n + 1) g5 g4 g3 g2 g1 g0 s (3n + 2) b5 b4 b3 b2 b1 b0 s (3n + 3) rgb arrangement output note: n= lower 8 bits of address (0 to 239) 1st transmission 2nd transmission 3rd transmission db 17 db 16 db 15 db 14 db 13 db 12 db 17 db 16 db 15 db 14 db 13 db 12 figure 5.1.3.1.8 80-system 8-bit interface (tri=1, dfm=1): 3 times transmission (65 k color) free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 25 5.1.3.2 rgb data transfer mode selection pd 17 pd 16 pd 15 pd 14 pd 13 pd 12 pd 11 pd 10 pd 9 pd 8 pd 7 pd 6 pd 5 pd 4 pd 3 pd 2 pd 1 pd 0 input data r5 r4 r3 r2 r1 r0 *s (3n + 1) / **s (720 - 3n) g5 g4 g3 g2 g1 g0 *s (3n + 2) / **s (719 - 3n) b5 b4 b3 b2 b1 b0 *s (3n + 3) / **s(718 - 3n) rgb arrangement output note: n= lower 8 bits of address (0 to 239) and *(a series in case of ss= ? 0") / ** (a series in case of ss= ? 1") figure 5.1.3.2.1 rgb-system 18-bit interface pd 17 pd 16 pd 15 pd 14 pd 13 pd 9 pd 11 pd 10 pd 8 pd 7 pd 6 pd 5 pd 4 pd 3 pd 2 pd 1 input data r5 r4 r3 r2 r1 r0 *s (3n + 1) / **s (720 - 3n) g5 g4 g3 g2 g1 g0 *s (3n + 2) / **s (719 - 3n) b5 b4 b3 b2 b1 b0 *s (3n + 3) / **s (718 - 3n) rgb arrangement output note: n= lower 8 bits of address (0 to 239) and *(a series in case of ss= ? 0") / ** (a series in case of ss= ? 1") figure 5.1.3.2.2 rgb-system 16-bit interface pd 17 pd 16 pd 15 pd 14 pd 13 pd 12 input data r5 r4 r3 r2 r1 r0 s (3n + 1) g5 g4 g3 g2 g1 g0 s (3n + 2) b5 b4 b3 b2 b1 b0 s (3n + 3) rgb arrangement output note: n= lower 8 bits of address (0 to 239) 1st transmission 2nd transmission 3rd transmission pd 17 pd 16 pd 15 pd 14 pd 13 pd 12 pd 17 pd 16 pd 15 pd 14 pd 13 pd 12 figure 5.1.3.2.3 rgb-system 6-bit interface free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 26 5.1.3.3 command transfer mode selection the transfer type differs according to the 18-/16-/9-/8-bit interface. db 17 input data instruction bit (ib) db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 figure 5.1.3.3.1 68/80-system 18-bit interface db 17 input data instruction bit (ib) db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 figure 5.1.3.3.2 68/80-system 16-bit interface 1st transmission 2nd transmission db 17 input data instruction bit (ib) db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 figure 5.1.3.2.3 68/80-system 9-bit interface db 17 input data instruction bit (ib) db 16 db 15 db 14 db 13 db 12 db 11 db 10 ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 1st transmission 2nd transmission db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 figure 5.1.3.2.4 68/80-system 8-bit interface free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 27 5.2 interface specification the S6D1121 incorporates a system interface, which is used to set instructions, and two external display interfaces, which are used to display motion pictures. selecting these interfaces to match the screen data (motion picture or still picture) enables efficient transfer of data for display. 5.2.1 display operation mode the external display interfaces include rgb interface and vsync interface. this allows flicker-free screen update. when rgb interface is selected, the synchronization signals (vsync, hsync, and dotclk) are available for use in operating the display. the data for display (pd17-0) is written according to the values of the data enable signal (enable) in synchronization with the vsync, hsync, and dotclk signals. in addition, using the window address function enables rewriting only to the internal ram area to display motion pictures. using this function also enables simultaneously display of the motion picture area and the ram data that was written. the internal display operation is synchronized with the frame synchronization signal (vsync) in vsync interface mode. w hen writing to the internal ram is done within the required time after the falling edge of vsync, motion pictures can be displayed via the conventional interface. there are some limitations on the timing and methods of writing to ram. the S6D1121 has four operation modes for each display state. these settings are specified by control instructions for external display interface. transitions between modes should follow the transition flow. table 5.2.1.1 display operation mode, ram access selection and display operation synchronization operation mode ram access selection (rm) display operation mode (dm1-0) display operation synchronization internal clock operation (displaying still picture) system interface (rm=0) internal clock operation (dm1-0=00) osc rgb interface (displaying motion pictures) rgb interface (rm=1) rgb interface (dm1-0=01) vsync, hsync, dotclk vsync interface (displaying motion pictures) system interface (dm1-0=10) vsync interface (rm=0) osc mddi interface (displaying motion pictures) system interface (rm=0) mddi interface (dm1-0=00,10) osc notes: 1) instruction registers can only be set via system interface. 2) switching among rgb and vsync interface cannot be done. 3) rgb interface and mddi interface cannot be used at the same time. 4) rgb interface mode cannot be set during operations. 5) for mode transitions, see the section on the rgb display interface. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 28 5.2.2 6800/80 system interface 5.2.2.1 80-series parallel interface the mcu uses a 12-wires 8-data parallel interface or 13-wires 9-data parallel interface or 20-wires 16-data parallel interface or 22-wires 18-data parallel interface. the chip-select csb (activ e low) enables and disables the parallel interface. resetb (acti ve low) is an external reset signal. rw_wrb is the parallel data write, e_rdb is the parallel data read and db [17:0] is parallel data. the graphics controller chip reads the data at the rising edge of rw_wrb signal. the rs of an external signal is the data/command flag. when rs=?1?, db [17:0] bits are index parameter s or display ram data. when rs =?0?, d [17:0] bits are index command. the 80-series bi-directional interface can be used for communication between the micro controller and lcd driver chip. write cycle sequence the write cycle means that the host writes information (command or/and data) to the display via the interface. each write cycle (rw_wrb high-low-high sequence) consists of 3 controls (rs, e_rdb, rw_wrb_wrb) and data signals (db [17:0]). rs is a control signal, which tells if the data is an index command or a data. read cycle sequence the read cycle (e_rdb high-low-high sequence) means that the host reads information from display via interface. the display sends data (db [17:0]) to the host when there is a falling edge of e_rdb and the host reads data when there is a rising edge of e_rdb . figure 5.2.2.1.1 80-series interface data bus status (data read and write) free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 29 5.2.2.2 6800-series parallel interface the mcu uses a 12-wires 8-data parallel interface or 13-wires 9-data parallel interface or 20-wires 16-data parallel interface or 22-wires 18-data parallel interface. the chip-select csb (activ e low) enables and disables the parallel interface. resetb (acti ve low) is an external reset signal. the e_rdb is the read/write flag and db [17:0] is parallel data. the graphics controller chip reads the data at the falling edge of e_rdb signal when rw_wrb = ?1? and writes the data at the falling of the e_rdb signal when rw_wrb =?0?. the rs is the data/command flag. when rs =?1?, db [17:0] bits are display ram data. when rs = ?0?, db [17:0] bits are index command. the 6800-series bi-directional interface can be used for communication between the micro controller and lcd driver chip. write cycle sequence the write cycle means that the host writes information (command or/and data) to the display via the interface. each write cycle (e_rdb low-high-low sequence) consists of 3 control signals (rs, e_rdb, rw_wrb) and data signals (db [17:0]). rs is a control signal, which tells if the data is a index command or a data. read cycle sequence the read cycle (e_rdb high-low-high sequence) means that the host reads information from display via interface. the display sends data (db [17:0]) to the host when there is a falling edge of e_rdb and the host reads data when there is a rising edge of e_rdb . figure 5.2.2.2.1 6800-series interface data bus status (data read and write) free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 30 5.2.2.3 acess to display data ram and internal registers below figures show read/write accesses to the display data ra m and write accesses to internal registers 8-bit, 9-bit, 16-bit an d 18-bit parallel interface modes. figure 5.2.2.3.1 read/write in 16-/18-bit parallel interface (80-series) note: while setting the writing to a display ram, set it the fixed input of the high level to rs pin. while setting the writing to a display data ram, in the case of 16-/18-bit parallel interface, 1 cycle period of write cycle is pointed out. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 31 5.2.3 serial interface the S6D1121 allows serial interface transfer, using the chip select line (csb), serial transfer clock line (scl), register sel ect line (rs), serial input data (sdi), and serial output data (sdo). for a serial interface, the im0/id pin function uses an id pin. the S6D1121 initiates serial data transfer by transferring the start byte at the falling edge of csb input. it ends serial data transfer at the rising edge of csb input. the S6D1121 is selected when the 6-bit chip address in the start byte matches the 6-bit device identification code that is assigned to the S6D1121. when selected, the S6D1121 receives the subsequent data string. the id pin can determine the lsb of the identification code. the five upper bits must be 01110. two different chip addresses must be assigned to a single S6D1121 because the seventh bit of the start byte is used as a address select bit (da): when da = 0, data can be written to the index register or status can be read, and when da = 1, an instruction can be issued or data can be written to or read from ram. read or write is selected according to the eighth bit of the start byte (rw_wrb bit). the data is received when the rw_wrb bit is 0, and is transmitted when the r/w bit is 1. after receiving the start byte, the S6D1121 receives or transmits the subsequent data byte-by-byte. the data is transferred wit h the msb first. the data after start byte consists of 16 bits (d15-0). two bytes are received with the msb first and the instruc tions are internally executed. after the start byte has been received, the next bytes are fetched of which, the first byte is fetched as the upper eight bits of d15-0 and the second byte is fetched as the lo wer eight bits of d15-0. assignment into d15-0 is described i n figure 5 .2.3.1.3 . three bytes of ram read data after the start byte are invalid. the S6D1121 starts to read correct ram data from the fourth byte . table 5.2.3.1 start byte format transfer bit 1 st 2 nd 3 rd 4 th 5 th 6 th 7 th 8 th device identification code start byte format 0 1 1 1 0 id rs rw_wr b note: the im [0] pin is used as id table 5.2.3.2 rs bit and rw_wrb bit function rs bit rw_wrb bit function 0 0 set index register 0 1 read status 1 0 writes instruction or ram data 1 1 reads instruction or ram data free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 32 5.2.3.1 serial interface data format serial data is processed by 16-bit interface. figure 5.2.3.1.1 instruction format for serial data transfer figure 5.2.3.1.2 ram data write format for serial data transfer serial interface timing diagram figure 5.2.3.1.3 basic timing diagram of data transfer through serial interface figure 5.2.3.1.4 timing diagram of consecuti ve ram data-write through serial interface free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 33 figure 5.2.3.1.5 timing diagram of register / status read through serial interface figure 5.2.3.1.5 timing diagram of ra m-data read through serial interface figure 5.2.3.1.7 timing diagram of register write through serial interface figure 5.2.3.1.8 timing diagram of register read through serial interface free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 34 figure 5.2.3.1.9 timing diagram of consecutive ram data-read through serial interface free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 35 5.2.4 rgb interface S6D1121 incorporates rgb interface to display not only still pictures but also motion pictures and gram to store data for displ ay. the rgb interface is performed in synchronization with vsync, hsync, and dotclk. combining the function of the high- speed write mode and the window address enables transfer only the screen to be updated and reduce the power consumption. table 5.2.4.1 rim bits rim1 rim0 rgb interface pd pin 0 0 18-bit rgb interface pd17 to 0 0 1 16-bit rgb interface pd17 to13, 11 to 1 1 0 6-bit rgb interface pd17 to12 1 1 setting disabled - the relationship between epl and enable signal is shown below. when enable is not active, the address is not update. when enable is active, the address is updated. table 5.2.4.1 relationship between epl and enable epl enable ram write ram address 0 0 valid updated 0 1 invalid hold 1 0 invalid hold 1 1 valid update the below figure shows the rgb interface timing with enabl signal. window address function enables transfer only the screen to be updated and reduce the power consumption. this function must be setting the window address for window display area. figure 5.2.4.1 rgb interface note: for rgb interface, vsync, hsync, dotclk should be supplied at much higher resolution than that of panel. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 36 5.2.4.1 rgb interface timing time chart for rgb interface is shown below. (in case of epl = 0) vsync hsync dotclk enable pd17-0 1- frame back porch period front porch period 1h vsync hsync dotclk enable pd17-0 valid data hlw 1clk 1 clk dtst hlw 1h figure 5.2.4.1.1 16-/18-bit rgb interface timing (in case of epl = 0, dpl = 0, vspl = 0, hspl = 0) vlw: the period in which vsync is ?low? level hlw: the period in which hsync is ?low? level dtst: set up time of data transfer free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 37 vsync hsync dotclk enable pd17-12 1- frame back porch period front porch period 1h vsync hsync dotclk enable pd17-12 valid data hlw 3clk 1 clk dtst hlw 1h valid data rgb rgbrgb rgbrgb figure 5.2.4.1.2 6-bit rgb interface timing (in case of epl = 0, dpl = 0, vspl = 0, hspl = 0) vlw: the period in which vsync is ?low? level hlw: the period in which hsync is ?low? level dtst: set up time of data transfer notes : 1. three clocks are regarded as one clock for transfer when data is transferred in 6-bit interface. 2. vsync, hsync, enable, dotclk and pd17-12 should be transferred in units of three clocks. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 38 5.2.4.2 transfer synchronization figure 5.2.4.2.1 transfer synchronizati on function in 6-bit rgb interface mode notes: 1. transfer synchronization function for a 6-bit bus interface. the S6D1121 has the transfer counter to count 1st, 2nd and 3rd data transfer in the 6-bit bus interface. the transfer counter is reset on the falli ng edge of vsync and enters the 1st data transmission state. tra nsfer mismatch can be corrected, and after that the transfer restarts correctly. in this method, when data such as displaying motion pictures is consecutively transferred, the effect of transfer mismatch is reduced and normal operation is recovered. 2. the internal display is operated in units of three dotclk. when the dotclk is not input in units of pixels, clock mismatch o ccurs and the frame, which is operated, and the next frame is not displayed correctly. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 39 5.2.4.3 usage on rgb display interface when external display interface is in use, the following functions are not available. table 5.2.4.3.1 external display interface and internal display operation function external (rgb) display interface internal display operation partial display cannot be used can be used scroll function cannot be used can be used 2 interlace driving cannot be used can be used 1. vsync, hsync, and dotclk signals should be supplied during display operation via rgb interface. 2. please make sure that when setting bits ecs3-0 in rgb interface, the clock on which operations are based changes from the internal operating clock to dotclk. 3. rgb data are transferred for three clock cycles in 6-bit rgb inte rface. data transferred, therefore, should be transferred i n units of rgb. 4. interface signals, vsync, hsync, dotclk, enable and pd17-0 should be set in units of rgb (pixels) to match rgb transfer. 5. during the period between the completion of displaying one frame data and the next vsync signal, the display will remain for a front porch period. an address set is done on the falling edge of vsync every frame in rgb interface. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 40 5.2.5 vsync interface the S6D1121 incorporates vsync interface, which enables motion pictures to be displayed with only the conventional system interface and the frame synchronization signal (vsync). this interface requires minimal changes from the conventional system to display motion pictures. figure 5.2.5.1 vsync interface 18bit / 16bit (80 systems) when dm1-0=?10? and rm=?0?, vsync interface is available. in th is interface the internal display operation is synchronized with vsync. data for display is written to ram via the system interface with higher speed than for internal display operation. this method enables flicker-free display of motion pictures with the conventional interface. display operation can be achieved by using the internal clock generated by the internal oscillator and the vsync input. since, all the data for display is written to ram, only the data to be rewritten is transferred. this method reduces the amount of data transferred during motion picture display operation. figure 5.2.5.2 motion picture data transfer via vsync interface vsync interface requires taking the minimum speed for ram writing via the system interface and the frequency of the internal clock into consideration. ram writing should be performed with higher speed than the result obtained from the calculation shown below. the internal memory writing address counter is reset by vsync. so, ensure interval time between vsync falling and gram data writing. the minimum interval time is 2 raster rows, and hence the data writing should start only after that duration . free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 41 ------------------------------------------------------------------------------------------------------------------------------- ---------------------------- internal clock frequency (fosc) [hz] = frame freq. (display raster-row (nl) + front porch (fp) + back porch (bp)) 43-clock fluctuation minimum speed for ram writing [hz] > 240 display raster-row (nl) / {((back porch (bp) + display raster-row (nl) ? margin) 43 clock) / fosc} note: when ram writing does not start immediately after the falling edge of vsync, the time between the falling edge of vsync and the ram writing start timing must also be considered. an example is shown below. example: display size 240rgb 320 raster-rows display line number 320 raster-row (nl=100111) back/front porch 4 lines/4 lines (bp=0100/fp=0100) frame frequency 70hz internal clock frequency (fosc) [hz] = 70 hz (320 + 4 + 4) lines 43 clock 1.1 / 0.9 = 1.2 mhz notes : 1.calculating the internal clock frequency requires considering the fluctuation. in the above case a 10% fluctuation within the vsync period is assumed. 2.the fluctuation includes lsi production variation and air temperature fluctuation. other fluctuations, including those for th e external resistors and the supplied power, are not included in this example. please keep in mind that a margin for these factors is also needed. minimum speed for ram writing [hz] > 240 320 / {((8 + 320 ? 2) lines 43 clock) / 1.2mhz} = 6.57 mhz notes: 1. in this case ram writing starts immediately after the falling edge of vsync. 2. the margin for display raster-row should be two raster-rows or more at the completion of ram writing for one frame. therefore, when ram writing starts immediately after the falli ng edge of vsync is performed at 6.57 mhz or more, the data for display can be rewritten before display operation has started. this means that flicker-free display operation is achieved. figure 5.2.5.3 operation for vsync interface free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 42 5.2.5.1 usage on vsync interface when external display interface is in use, the following functions are not available. table 5.2.5.1.1 external display interface and internal display operation function external (vsyn if) display interface internal display operation partial display cannot be used can be used scroll function cannot be used can be used 2 interlace driving cannot be used can be used 1. the example above is a calculated value. please keep in mind that a margin for these factors is also needed. the reason of production variation of the internal oscillator requires consideration. 2. the example above is a calculated value of rewriting the whole screen. a limitation of the motion picture area generates a margin for the ram write speed. vsync [line] 320 0 executed line back porch 4h vsync ram write(10mhz) 76800 times ram write 6.57 mhz rc oscillation 10% displaying operation min. 2h displaying operation ram write displaying operation min. 2h min. 2h (20-lines) moving picture display (280-lines) back porch (4-lines) 300 20 (20-lines) front porch (4-lines) 14.08 (70hz) figure 5.2.5.1.1 limitation of motion picture area 3. during the period between the completion of displaying one frame data and the next vsync signal, the display will remain for a front porch period. 4. transition between the internal operating clock mode (dm1-0=?00?) and vsync interface mode will be valid after the completion of the screen, which is displayed when the instruction is set. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 43 address setting vsync interface mode setting (dm1-0=10, rm=0) index register setting(r22h) wait more than 1 frame vsync interface ram data writing vsync interface operation internal clock mode setting (dm1-0=00, rm=0) wait more than 1 frame internal clock operation internal clock operation display operation in synchronization with the internal clock the value set in dm1- 0 and rm1-0 will be valid after completion of 1-frame display. display operation in synchronization with vsync note: when the interface mode is switched, vsync should be input before setting dm1-0 and rm bit. internal clock operation =>vsync interface wait more than 1 frame internal clock mode setting (dm1-0=00, rm=0) internal clock operation vsync interface operation display operation in synchronization with vsync the value set in dm1- 0 and rm1-0 will be valid after completion of 1-frame display. display operation in synchronization with the internal clock note: when switching to internal clock mode, please keep supplying vsync signal for more than 1 frame. vsync interface => internal clock operation figure 5.2.5.1.2 transition between the internal operating clock mode and vsync interface mode 5. partial display, vertical scroll, and interlaced driving functions are not available on vsync interface mode. 6. the flow of above method performs the vsync interface mode. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 44 5.2.6 mddi (mobile display digital interface ) 5.2.6.1 introdiuction of mddi the S6D1121 supports mddi. the mddi is a differential and serial interface with high speed. both command and image data transfer can be achieved with mddi. mddi host and client are linked with data and stb line. through data line, command or image data is transferred from mddi host to mddi client, and vice versa. data is transferred by packet unit. through stb line, strobe signal is transferred. when the link is in ?forward direction?, data is transferred from host to clien t; in ?reverse direction?, client transfer reverse data to mddi host. figure 5.2.6.1.1 physical connection of mddi host and client 5.2.6.2 data-stb encoding data is encoded using a data-stb method. data is carried over a bi-directional differential cable, while stb is carried over a unidirectional differential cable driven only by the host. figure below illustrates how the data sequence ?1110001011? is transmitted using data-stb encoding. figure 5.2.6.2.1 data-stb encoding free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 45 the following figure shows a sample circuit to generate data and stb from input data, and then recover the input data from data and stb. figure 5.2.6.2.2 data / stb generation and recovery circuit 5.2.6.3 mddi data-stb the data (mdp/mdn) and stb (msp/msn) signals are always operated in a differential mode to maximize noise immunity. each differential pair is parallel-terminated with the characteristic impedance of the cable. all parallel-terminations are in the c lient device. figure below illustrates the configuration of the drivers, receivers, and terminations. the driver of each signal pair has a differential current output. while receiving mddi packets the mddi_data and mddi_stb pairs use a conventional differential receiver with a differential voltage threshold of zero volts. in the hibernation state the driver outputs are disabled and the parallel termination resistors pull the differential voltage on each signal pair to zero volts. during hibernation a special receiver on the mddi_data pairs has an offset input differential voltage threshold of positive 125 mv, which causes the hibernation line receiv er to interpret the un-driven signal pair as logic-zero level. stb(host) data (host to client) enable(host) data (client to host) wake-up (client to host) host v t = 0 v t = 125mv mddi stb+ mddi stb- mddi data+ mddi data- client stb(client) v t = 0 v t = 0 r term r term v t = 125mv enable(client) data (host to client) data (client to host) wake-up (host to client) figure 5.2.6.3.1 differential connection between host and client free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 46 5.2.6.4 hibernation and wake_up S6D1121 support hibernation mode for reducing interface power consumption. the mddi link can enter the hibernation state quickly and wake up from hibernation quickly. this allows the system to force the mddi link into hibernation frequently to redu ce power consumption. in hibernation mode, hi-speed transceivers and receivers are disabled and low-speed & low-power receivers are enabled to detect wake-up sequence. stb(host) data (host to client) enable(host) data (client to host) wake-up (client to host) host off off off v t = 0 v t = 125mv mddi stb+ mddi stb- mddi data+ mddi data- client stb(client) off v t = 0 off v t = 0 r term r term v t = 125mv enable(client) data (host to client) data (client to host) wake-up (host to client) on on off figure 5.2.6.4.1 mddi transceiver and receiver state in hibernation when the link wakes up from hibernation the host and client exchange a sequence of pulses. these pulses can be detect using low-speed, low-power receivers that consume only a fraction of the current of the differential receivers required to receive th e signals at the maximum link operating speed. both the client and the host can wake up the link, so 2-types of wake-up are supported in S6D1121: host-initiated link wakeup and client-initiated link wakeup. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 47 5.2.6.5 mddi link wake up procedure rules for entering the hibernation state : the host sends 64 mddi_stb cycles after the crc of the link shutdown packet. also after this crc the host shall drive mddi_data0 to a logic-zero level and disable the mddi_data0 output of the host in the range of after the rising edge of the 16 th mddi_stb cycle to before the rising edge of the 48 th mddi_stb cycle (including output disable propagation delays). the host shall finish sending the 64 mddi_stb cycles after the crc of the link shutdown packet before it initiates the wake-up sequence. the client shall wait until after the rigins edge of the 48 th mddi_stb cycle after the crc of the link shutdown packet or later before it drives mddi_data0 to a logic-one level to attempt to wake-up the host. the client shall place its high-speed receivers for mddi_data0 and mddi_stb into hibernation any time after the rising edge of the 48 th mddi_stb cycle after the crc of the link shutdown packet. it is recommended that the client place its high-speed mddi_data0 and mddi_stb receivers into hibernation before the rising edge of the 64 th mddi_stb cycle after the crc of the link shutdown packet. rules for wake-up from the hibernation state : when the client needs service from the host it generates a request pulse by driving mddi_data0 to a logic-one level for 70 to 1000sec while mddi_stb is inactive and keeps mddi_data0 driven to a logic-one level for 70 mddi_stb cycles(range of 60 to 80) after mddi_stb becomes active. then the client disables the mddi_data0 driver by placing it into a high-impedance state. if mddi_stb is active during hibernation(which is unlikely, but allowed per the spec) then the client may only drive mddi_data0 to a logic one level for 70 mddi_stb cycles (range of 60 to 80). this action causes the host to restart data traffic on the forwar d link and to poll the client for its status. the host shall detect the presence of the request pulse from the client (using the low-power differential receiver with a +125m v offset) and begin the startup sequence by first driving mddi_stb to a logic-zero level and mddi_data0 to a logic-high level for at least 200nsec, and then while toggling mddi_stb it shall continue to drive mddi_data0 to a logic-one level for 150 mddi_stb cycles (range of 140 to 160) and to logic-zero for 50 mddi_stb cy cles. the client shall not send a service request pulse if it detects mddi_data0 at a logic-one level for more than 80 mddi_stb cycles. after the client has detected mddi_data0 at a logic- one level for 60 to80 mddi_stb cycles it shall begin to search for the interval where drives mddi_data0 to a logic-zero level f or 50 mddi_stb cycles then the host starts sending packets on the link. the first packet sent shall be a sub-frame header packet. the client begins to look for the sub-frame header packet after m ddi_data0 is at a logic-zero level for 40 mddi_stb cycles of t he 50 cycle interval. the host may initiate the wake-up by first enabling mddi_stb and simultaneously drive it to a logic-zero level. mddi_stb shall not be driven to a logic-one level until pulses are output as described below. after mddi_stb reaches a valid logic-zero level the host shall enable mddi_data0 and simultaneously drive it to a logic-one level. mddi_data0 shall not be driven to a logic-zero level during the wake-up process until the interval where it is driven to a logic-zero level for an interval of 50 mddi_stb pulses as described below. the host shall wait at least 200 nsec after m ddi_data0 reaches a valid logic-one level before driving pulses o n mddi_stb. this timing relationship shall always occur while considering the worst-case output enable delays. this guarantees that the client has sufficient time to fully enable its mddi_stb receiver after being woken up by a logic-one level on mddi_dat a0 that was driven by the host. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 48 figure 5.2.6.5.1 process from entering hibernation to exiting hibernation free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 49 5.2.6.6 host-initiated link wake-up procedure the simple case of a host-initiated wake-up is described below without contention from the client trying to wake up at the same time. the following sequence of events is illustrated in the following figure. figure 5.2.6.6.1 host-initiated link wakeup sequence i the detailed descriptions for labeled events are as follows: a. the host sends a link shutdown packet to inform the client that the link will transition to the low-power hibernation state. b. following the crc of the link shutdown packet the host toggles mddi_stb for 64 cycles to allow processing in the client to finish before it stops mddi_stb from toggling which stops the re covered clock in the client device. also during this interval t he host initially sets mddi_data0 to a logic-zero level, and then disables the mddi_data0 output in the range of 16 to 48 mddi_stb cycles (including output disable propagation delays) after the crc. it may be desirable for the c lient to place its high-speed receivers for mddi_data0 and mddi_stb into a low power state any time after 48 mddi_stb cycles after the crc and before point c. c. the host enters the low-power hibernation state by disabling the mddi_data0 and mddi_stb drivers and by placing the host controller into a low-power hibernation state. it is also allowabl e for mddi_stb to be driven to logic-zero level or to continu e toggling during hibernation. the client is also in the low-power hibernation state. d. after a while, the host begins the link restart sequence by enabling the mddi_data0 and mddi_stb driver outputs. the host drives mddi_data0 to a logic-one level and mddi_stb to logic-zero level for at least the time it takes for the drivers to fully enable their outputs. the host shall wait at least 200 nsec after mddi_data0 reaches a valid logic-one level and mddi_stb reaches a valid logic-zero level before driving pulses on mddi_stb. this gives the client sufficient time to prepare to receive high-spee d pulses on mddi_stb. the client first detects the wake-up pulse using a low-power differential receiver having a +125mv input offset voltage. e. the host drivers are fully enabled and mddi_data0 is being driv en to a logic-one level. the host begins to toggle mddi_stb i n a manner consistent with having a logic-zero level on mddi_data0 for a duration of 150 mddi_stb cycles. f. the host drives mddi_data0 to logic-zero level for 50 mddi_stb cycles. the client begins to look for the sub-frame header packet after mddi_data0 is at logic-zero level for 40 mddi_stb cycles. g. the host begins to transmit data on the forward link by sending a sub-frame header packet. beginning at point g the mddi host generates mddi_stb based on the logic level on mddi_data0 so that proper data-strobe encoding commences from point g. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 50 figure 5.2.6.6.2 host-initiated link wakeup sequence ii free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 51 5.2.6.7 client initiated link wake-up procedure an example of a typical client-initiated service request event with no contention is illustrated in the following figure. figure 5.2.6.7.1 client-initiated link wakeup sequence the detailed descriptions for labeled events are as follows: a. the host sends a link shutdown packet to inform the client that the link will transition to the low-power hibernation state. b. following the crc of the link shutdown packet the host toggles mddi_stb for 64 cycles to allow processing in the client to finish before it stops mddi_stb from toggling which stops the re covered clock in the client device. also during this interval t he host initially sets mddi_data0 to a logic-zero level, and then disables the mddi_data0 output in the range of 16 to 48 mddi_stb cycles (including output disable propagation delays) after the crc. it may be desirable for the c lient to place its high-speed receivers for mddi_data0 and mddi_stb into a low power state any time after 48 mddi_stb cycles after the crc and before point c. c. the host enters the low-power hibernation state by disabling it s mddi_data0 and mddi_stb driver outputs. it is also allowabl e for mddi_stb to be driven to logic-zero level or to continue toggling during hibernation. the client is also in the low-power hibernation state. d. after a while, the client begins the link restart sequence by enabling the mddi_stb receiver and also enabling an offset in its mddi_stb receiver to guarantee the state of the received version of mddi_stb is a logic-zero level in the client before the hos t enables its mddi_stb driver. the client will need to enable the offset in mddi_stb immediately before enabling its mddi_stb receiver to ensure that the mddi_stb receiver in the client is always receiving a valid differential signal and to prevent erro neous received signals from propagating into the client. after that, the client enables its mddi_data0 driver while driving mddi_data 0 to a logic-one level. it is allowed for mddi_data0 and mddi_stb to be enabled simultaneously if the time to enable the offset and enable the standard mddi_stb differential receiver is less than 200 nsec. e. within 1 msec the host recognizes the service request pulse, and the host begins the link restart sequence by enabling the mddi_data0 and mddi_stb driver outputs. the host drives mddi_d ata0 to a logic-one level and mddi_stb to a logic-zero level for at least the time it takes for the drivers to fully enable their outputs. the host shall wait at least 200 nsec after mddi_ data0 reaches a valid logic-one level and mddi_stb reaches a valid full y-driven logic-zero level before driving pulses on mddi_stb. this gives the client sufficient time to prepare to receive high-speed pulses on mddi_stb. f. the host begins outputting pulses on mddi_stb and shall keep mddi_data0 at a logic-one level for a total duration of 150 mddi_stb pulses through point h. the host generates mddi_stb in a manner consistent with sending a logic-zero level on mddi_data0. when the client recognizes the first pulse on mddi_stb it shall disable the offset in its mddi_stb receiver. g. the client continues to drive mddi_data0 to a logic-one level for 70 mddi_stb pulses, and the client disables its mddi_data0 driver at point g. the host continues to drive mddi_data0 to a logic-one level for duration of 80 additional mddi_stb pulses, a nd at point h drives mddi_data0 to logic-zero level. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 52 h. the host drives mddi_data0 to logic-zero level for 50 mddi_stb cycles. the client begins to look for the sub-frame header packet after mddi_data0 is at logic-zero level for 40 mddi_stb cycles. after asserting mddi_data0 to logic-zero level and driving mddi_stb for duration of 50 mddi_stb pulses the host begin s to transmit data on the forward link at point i by sending a sub-frame header packet. the client begins to look for the sub- frame header packet after mddi_data0 is at logic-zero level for 40 mddi_stb cycles. it will be possible when transferring a command, frame memory data or multiple parameter data to invoke a pause in the data transmission. if the chip select line is released after a whole byte of a frame memory data or multiple parameter data has been completed, then S6D1121 will wait and continue the frame memory data or parameter data transmission from the point where it was paused. if the chip select line is released after a whole byte of a command as been completed, then the display module will receive either the command?s parameters (if appropriate) or a new command when the chip select line is next enabled as shown below. figure 5.2.6.7.2 client-initiated wakeup sequence S6D1121 supports 1-type of client-initiated link wake-up: vsy nc based link wake-up. as client-initiated wake-up action is executed in hibernation state only, register setting for each wake-up have to be set before link shut-down. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 53 vsync based link wake up: in display-on state, when the ic finishes displaying all internal gram data, data request must be transferred to mddi host for new video data. as mddi link is usually in hibernation for reducing interface power consumption, mddi link wake-up must be done before internal gram update. in that case, client initiated link wake-up can be used as data request. when vsync based link wake-up register (50h: vwake_en) is set, client initiated wake-up is executed in synchronization with the vertical-sync signal which generated in S6D1121. usin g vsync based link wake-up, tearing-less display can be accomplished if interface speed and wake-up time is well known. the following figure shows detailed timing for vsync based link wake-up. figure 5.2.6.7.3 vsync based link wake-up procedure the detailed descriptions for labeled events are as follows: a. mddi host writes to the vsync based link wakeup register to enable a wake-up based on internal vertical-sync signal. b. link_active goes low when the host puts in the link into hibernation after no more data needs to be sent to the S6D1121. c. frame_update, the internal vertical-sync signal goes high indicating that update pointer has wrapped around and is now readi ng from the beginning of the frame buffer. link wake-up point c an be set using wkf and wkl (51h) registers. wkf specifies the number of frame before wake-up; wkl specifies the number of lines before wake-up. d. client_wakeup input to the mddi client goes high to start the client initiated link wake-up. e. link_active goes high after the host brings the link out of hibernation. f. after link wake-up, client_wakeup signal and the vwake_en register are cleared automatically. it will be possible when transferring a command, frame memory data or multiple parameter data to invoke a pause in the data transmission. if the chip select line is released after a whole byte of a frame memory data or multiple parameter data has been completed, then S6D1121 will wait and continue the frame memory data or parameter data transmission from the point where it was paused. if the chip select line is released after a whole byte of a command as been completed, then the display module will receive either the command?s parameters (if appropriate) or a new command when the chip select line is next enabled as shown below. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 54 5.2.6.8 host-initiated wake-up from hibernation with connection from client this is actually a host-initiated wake-up, but we have included the case where the client also wants to wake up the link with t he latest possible request. the labeled events are: a. the host sends a link shutdown packet to inform the client that the link will transition to the low-power hibernation state. b. following the crc of the link shutdown packet the host toggles mddi_stb for 64 cycles to allow processing in the client to finish before it stops mddi_stb from toggling which stops the recovered clock in the client device. also during this interval the host disables the mddi_data0 output in the range of 16 to 48 mddi_stb cycles(including output disable propagation delays) after the crc. it may be desirable for the client to place its high-speed receivers for mddi_data0 and mddi_stb into a low power state any time after 48 mddi_stb cycles after the crc and before point c. c. the host enters the low-power hibernation state by disabling its mddi_data0 and mddi_stb driver outputs. it is also allowable for mddi_stb to be driven to a logic-zero level or to continue toggling during hibernation. the client is also in the low-power hibernation state. d. after a while, the host begins the link restart sequence by enabling the mddi_data0 and mddi_stb driver outputs. the host drives mddi_data0 to a logic-one level and mddi_stb to a logic-zero level for at least the time it takes for the drivers to fully enable their outputs. the host shall wait at least 200 nsec after mddi_data0 reaches a valid logic- one level and mddi_stb reaches a valid logic-zero level before driving pulses on mddi_stb. this gives the client sufficient time to prepare to receive high-speed pulses on mddi_stb. e. the host drivers are fully enabled and mddi_data0 is being driven to a logic-one level. the host begins to toggle mddi_stb in a manner consistent with having a logic-zero level on mddi_data0 for a duration of 150 mddi_stb cycles. f. at up to 70 mddi_stb cycles after point e the client has not yet recognized that the host is driving mddi_data0 to a logic-one level so the client also drives mddi_data0 to a logic-one level. this occurs because the client has a need to request service from the host and does not recognize that the host has already begun the link restart sequence. g. the client ceases to drive mddi_data0, and places its driver into a high-impedance state by disabling its output. the host continues to drive mddi_data0 to a logic-one level for 80 additional mddi_stb cycles. h. the host drives mddi_data0 to a logic-zero level for 50 mddi_stb cycles. the client begins to look for the sub-frame header packet after mddi_data0 is at a logic-zero level for 40 mddi_stb cycles. i. the host begins to transmit data on the forward link by sending a sub-frame header packet. beginning at point i the mddi host generates mddi_stb based on the logic level on mddi_data0 so that proper data-strobe encoding commences from point i. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 55 figure 5.2.6.8.1 host-initiated wake-up process from hibernation with connection from client free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 56 5.2.6.9 mddi packet mddi transfer data by packet format. mddi host can make many packets and transfer them. in S6D1121, several packets format is supported. most packets are transferred from mddi host to client (forward direction); but reverse encapsulation packet is transferred from mddi client to host (reverse direction). a number of packets, started by sub-frame header packet, construct 1 sub frame. figure 5.2.6.9.1 host-initiated wake-up process from hibernation with connection from client refer to mddi packet structure, sub-frame header packet is plac ed in front of a sub-frame, and some sub-frame construct media- frame together. the following table describes 9 types of packet which is supported in S6D1121. packet function direction sub-frame header packet header of each sub frame forward register access packet register setting forward video stream packet video data transfer forward filler packet fill empty packet space forward reverse link encapsulation packet reverse data packet reverse round-trip delay measurement packet host-> client->host delay check forward/reverse client capability packet capability of client check reverse client request and status packet information about client status reverse link shutdown packet end of frame forward sub-frame header packet: figure 5.2.6.9.2 sub-frame header packet structure free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 57 register access packet: figure 5.2.6.9.3 register access packet structure video stream packet: figure 5.2.6.9.4 video stream packet structure free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 58 filler packet: figure 5.2.6.9.5 filler packet structure link shutdown packet: figure 5.2.6.9.6 link shutdown packet structure : fixed value for more information about mddi packet, please refer to vesa mddi spec. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 59 5.2.6.10 mddi operating state in mddi, six operation modes are available. the following table describes six modes. state osc step-up circuit internal logic status mddi i/o wake-up by sleep on disabled display off mddi link hibernation hibernation driver on host ? initiated wait on disabled display off mddi link in sync standard driver on - normal on enabled display on mddi link in sync standard driver on - nap on disabled display off mddi link in sync standard driver on - idle on enabled display on mddi link hibernation hibernation driver on host ? initiated client ?initiated (vsync, gpio) stop off disabled display off mddi link off driver all off reset sleep: initial status when external power is connected to the ic. in this state, internal oscillator is operating, and mddi link is in hibernation state. as no command or signal is applied to the ic except reset input, internal logic or step-up circuit is off. wait: after the wake-up sequence, the ic is in wait state. mddi link is in sync, and internal logic or step-up is still off because no other register access or video stream packet is transferred to the ic. normal: mddi link, step-up circuit, and internal logic circuit is on. register access or video data transfer is available in normal state. idle: when no more video data update is needed, mddi link is in hibernation so that interface power can be reduced. internal step-up & logic circuits are still operating. mddi link wakeup will be accomplished when vsync wakeup register is set before hibernation or gpio interrupt is set. nap: this state is set by register access. step-up and internal logic is off, but mddi link is on. mddi link have to be in sync because the ic must receive commands for power save or normal operation stop: stop state is set by register access (r10h). in this state, mddi link, internal oscillator, step-up, and logic circuit are al l off. to release stop state, input reset signal. after reset, status is sleep state. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 60 system power on sleep system reset input - osc : osc on - step-up : disabled - mddi link : hibernation - logic : display off mddi link synchronization procedure - osc : osc on - step-up : disabled - mddi link : in sync - logic : display off - osc : osc on - step-up : enabled - mddi link : in sync - logic : display on 1) power setting using register packet 2) step-up enable sequence using register packet 3) frame buffer access using video packet 4) display on sequence using register packet wait power on normal idle - stop state setting using register packet (both standard & offset receiver disabled) - osc: osc on - step-up: enabled - mddi link:hibernation - logic: display on mddi link wa k e-u p! - vsync wakeup - gpio wakeup - host initiated wakeup nap - osc: osc on - step-up: disabled - mddi link: in sync - logic: display off stop - osc: osc off - step-up: disabled - mddi link:link disabled - logic: display off only reset signal is admitted for wake-up from stop state ! 1 3 2 nap state set sequence 1) display off sequence using register packet 2) nap state setting(slp=1) using register packet 1 idle state (when frame buffer update not needed) 1) vsync wakeup enable register setting (optional) 2) link shut-down using link shut-down packet (mddi link is in hibernation state) 3 nap state release sequence 1) nap state register disable 2) step-up enable sequence 3) frame buffer update (optional) 4) display on sequence 2 figure 5.2.6.10.1 operating state in mddi mode free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 61 5.2.6.11 tearing less display in S6D1121, the matching between data writing timing and written data display timing is important. if timing is mismatched, tea ring effect can occur. to avoid display tearing effect, two possible ways are suggested. first case is that data write is slower tha n speed of displaying written data. in this case, data write speed is not critical, but current consumption in interface will be increased because data transfer time is long. data write time is selected widely in this case. other case is that data write is faster th an speed of displaying written data. in this case, data update speed is very high so that transfer time is short. so current consumption in interface can be minimized, but it requires fast data transfer. the most important thing is to avoid data scan conflicts with data update. the following figures describe some examples to avoid display tearing phenomenon . display speed is faster than data write: figure 5.2.6.11.1 tearing-less display: display speed is faster than data write display speed is slower than data write: figure 5.2.6.11.1 tearing-less display: display speed is faster than display free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 62 5.2.7 sub panel control on mddi S6D1121 supports a sub panel control function which controls sub panel driver ic using 68-/80-mode protocol (csb, rs, rw_wrb and db). also supports on 80-mode protocol of stn type. when mddi host (base band modem) sends several packets to S6D1121, if the packet is for sub panel, the ic converts the packet to 68-/80-mode protocol and sends them to sub panel driver ic. so separated line for sub panel control are not needed. after all, S6D1121 enables the sub panel driver ic whi ch doesn?t support mddi to be applied to the system. S6D1121 supports only 68-/80-mode 18/16/9/8 bit format for sub panel control. lcd driver ic tft-lcd module (main display) tft-lcd module (sub display) lcd driver ic sub panel (normal ldi) msm (baseband modem) mddi host mddi trx/ rx 80 mode parallel i/f main panel (mddl-supported ldi) figure 5.2.7.1 schematic diagram of sub panel control function free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 63 5.2.7.1 main / sub panel selection using 53h register (53h address can be changed using sub_sel register), main / sub panel data path can be selected. when S6D1121 receives register access packet (initially 53h index) from mddi host, it decodes the packet and checks the last bit of the register data field is ?1? or ?0?. if the last bit is ?0?, the following register access packet or video stream packet is trans ferred to the sub panel control signal generation block. sub panel selection address (initially 53h) can be changed using sub_sel register. do not change the sub_sel value to previously occupied address. register address = sub_sel register data = 0000h register data = 0001h main panel selection procedure command transfer (register access packet) sub panel selection procedure video data transfer (video stream packet) register address = sub_sel command / data transfer to sub panel driver ic (80-mode protocol) note: initial value of sub_sel = 7ah figure 5.2.7.1.1 main / sub panel selection procedure when video data is transferred to the sub panel driver ic via S6D1121, additional gram access command (normally 22h on the sub panel driver ic) is automatically generated in S6D1121. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 64 5.2.7.2 sub panel timing 5.2.7.2.1 tft type sub panel timing register data transfer timing: if sub panel is selected, and sub panel type is tft, register se tting is executed like below figure. register data is transferr ed through s_db [17:10] and s_db [8:1] in 18/16 bit type. if 9/8 bit type is used, data is transferred thorough s_db [17:10]. refe r to sub panel control (15h index) section. c r c s_db[17:0] s_csb s_rs s_wrb 0000eh (index 07h) 00c1eh (030fh 16bit data) index write parameter write mddi data stream register address (0007h) header c r c register data (030fh) 1 register access packet figure 5.2.7.2.1.1 18/16 bit type register access data transfer in 9/8 bit mode, s_db [17:10] is used. in this mode, data is transferred at two times. first transfer is msb 8bit and second tr ansfer is lsb 8bit. c r c s_db[17:10] s_csb s_rs s_wrb index write parameter write mddi data stream register address (0007h) header c r c register data (030fh) 1 register access packet 00h (msb 8bit) 07h (lsb 8bit) 03h (msb 8bit) 0fh (lsb 8bit) figure 5.2.7.2.1.2 9/8 bit type register access data transfer free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 65 this figure shows register setting timing of 18/16 bit on the 68 mode. in the 68 mode, s_wrb must be connected to e_rdb of sub panel module. rw_wrb of sub panel module must be tied to vss. only S6D1121 writes data to sub panel module. c r c s_db[17:0] s_csb s_rs s_wrb 0000eh (index 07h) 00c1eh (030fh 16bit data) index write parameter write mddi data stream register address (0007h) header c r c register data (030fh) 1 register access packet figure 5.2.7.2.1.3 68 mode 18 bit register data transfer video data transfer timing: in the tft type sub panel, stn_en register in 15h index is ?0?, and if user wants to use 68-mode interface protocol, then mpu_mode is set to ?1?. 18/16/9/8 mode is selected as setting sub_im register. refer to 15h index description. this figure shows the 18 bit video data transfer on the 80 mode. header 00044h gram write enable (index 22h) gram write enable (22h index) pixel write c r c pixel data #1 (01abch) c r c 1 video stream packet( 18-bpp ) pixel data #2 (100ffh) pixel data #4 (000ffh) pixel data #3 (0ff00h) pixel data #5 (00001h) pixel data #1 01abch pixel data #2 100ffh pixel data #3 0ff00h pixel data #4 000ffh pixel data #5 00001h pixel write pixel write pixel write pixel write db[17:0] (data output to sub ldi) s_csb (chip select for sub ldi) s_rs (command / data select) s_wrb (write enable for sub ldi) mddi data stream figure 5.2.7.2.1.4 80 mode 18 bit video data transfer free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 66 this figure shows the 18 bit on the 68 mode, s_wrb must be connected to e_rdb of sub panel module. rw_wrb of sub panel module must be tied to vss. only S6D1121 writes data to sub panel module. figure 5.2.7.2.1.5 68 mode 18 bit video data transfer this figure shows 80-mode 16 bit video data transfer. header 00022h gram write enable (index 22h) gram write enable (22h index) pixel write c r c pixel data #1 (1abch) c r c 1 video stream packet( 16-bpp ) pixel data #2 (00ffh) pixel data #4 (01ffh) pixel data #3 (ff00h) pixel data #5 (0001h) pixel data #1 1abch pixel data #2 00ffh pixel data #3 ff00h pixel data #4 01ffh pixel data #5 0001h pixel write pixel write pixel write pixel write db[17:10],[8:1] (data output to sub ldi) s_csb (chip select for sub ldi) s_rs (command / data select) s_wrb (write enable for sub ldi) mddi data stream figure 5.2.7.2.1.6 80 mode 16 bit video data transfer free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 67 this figure shows 80-mode 9 bit video data transfer. header 044h gram write enable (22h index) pixel write c r c pixel data #1 (01abch) c r c 1 video stream packet( 18-bpp ) pixel data #2 (100ffh) pixel data #4 (000ffh) pixel data #3 (0ff00h) pixel data #5 (00001h) 00dh msb pixel write pixel write pixel write pixel write db[17:9] (data output to sub ldi) s_csb (chip select for sub ldi) s_rs (command / data select) s_wrb (write enable for sub ldi) mddi data stream 0bch lsb pixel data #1 080h msb 0ffh lsb pixel data #2 07fh msb 100h lsb 000h msb 0ffh lsb pixel data #3 pixel data #4 gram write enable 044h 000h msb 001h lsb pixel data #5 figure 5.2.7.2.1.7 80 mode 9 bit video data transfer this figure shows 80-mode 8 bit video data transfer. header 22h gram write enable (22h index) pixel write c r c pixel data #1 (1abch) c r c 1 video stream packet( 16-bpp ) pixel data #2 (00ffh) pixel data #4 (01ffh) pixel data #3 (ff00h) pixel data #5 (0001h) 1ah msb pixel write pixel write pixel write pixel write db[17:10] (data output to sub ldi) s_csb (chip select for sub ldi) s_rs (command / data select) s_wrb (write enable for sub ldi) mddi data stream bch lsb pixel data #1 00h msb ffh lsb pixel data #2 ffh msb 00h lsb 01h msb ffh lsb pixel data #3 pixel data #4 gram write enable 22h 00h msb 01h lsb pixel data #5 figure 5.2.7.2.1.8 80 mode 8 bit video data transfer free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 68 5.2.7.2.2 stn type sub panel timing register data transfer timing: this figure shows conventional type stn mode register data setting. conventional type does not include parameter. instruction type is only 8bit. to use stn type, stn_en is set to ?1?. in stn type, S6D1121 controls s_rs pin using register address [0] in register access packet. register address [0] is ?0?, then s_rs is set to ?0?, and register address [0] is ?1?, s _rs is set to ?1?. refer to sub panel control (15h index) section. 00002h (0001h parameter) 000aah (55h index) c r c s_db[17:0] s_csb s_rs s_wrb index write mddi data stream register address (0000h) header c r c register data (0055h) 1 register access packet c r c register address (0000h) header c r c register data (0001h) parameter write figure 5.2.7.2.2.1 80 mode stn type conventional register instruction this type is used to include parameter. when instruction is transferred, s_rs is zero, and when parameter is transferred, s_rs is ?1?. s_rs is controlled using register address [0] of register access packet. 000aah (55h index) 00002h (0001h parameter) c r c s_db[17:0] s_csb s_rs s_wrb index write mddi data stream register address (0000h) header c r c register data (0055h) 1 register access packet c r c register address (0001h) header c r c register data (0001h) parameter write (rs = 1) figure 5.2.7.2.2.2 80 mode stn type included parameter free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 69 video data transfer timing: in stn mode, video data start register (like 22h is tft mode) does not need generally. but some stn type needs video data start register. if those types of stn ddi are used, user has to set the register index. this figure shows stn 16 bit mode video data transfer . header 00044h (write disabled) pixel write c r c pixel data #1 (01abch) c r c 1 video stream packet( 18-bpp ) pixel data #2 (100ffh) pixel data #4 (000ffh) pixel data #3 (0ff00h) pixel data #5 (00001h) pixel data #1 01abch pixel data #2 100ffh pixel data #3 0ff00h pixel data #4 000ffh pixel data #5 00001h pixel write pixel write pixel write pixel write db[17:0] (data output to sub ldi) s_csb (chip select for sub ldi) s_rs (command / data select) s_wrb (write enable for sub ldi) mddi data stream figure 5.2.7.2.2.3 80 mode stn type 16 bit video data transfer this figure shows stn 8bit mode video data transfer. if stn video data is 16bit mode, data transfer is executed during 2 times. fist transfer is msb 8bits, and second is lsb 8bits. header 22h pixel write c r c pixel data #1 (1abch) c r c 1 video stream packet( 16-bpp ) pixel data #2 (00ffh) pixel data #4 (01ffh) pixel data #3 (ff00h) pixel data #5 (0001h) 1ah msb pixel write pixel write pixel write pixel write db[17:10] (data output to sub ldi) s_csb (chip select for sub ldi) s_rs (command / data select) s_wrb (write enable for sub ldi) mddi data stream bch lsb pixel data #1 00h msb ffh lsb pixel data #2 ffh msb 00h lsb 01h msb ffh lsb pixel data #3 pixel data #4 22h write disabled 22h 00h msb 01h lsb pixel data #5 figure 5.2.7.2.2.4 80 mode stn type video data transfer free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 70 5.2.7.2.3 change data path from sub panel to main panel / figure 5.2.7.2.3.1 handover timing from sub panel to main panel free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 71 5.2.7.3 mddi intergrated system structure mddi support display system which incorporates gpio and sub panel control is seen below. S6D1121 can display to a maximum of qvga (240x320) resolution and sub panel resolution can be chosen according to the system requirement. figure 5.2.7.3.1 mddi-integrated system structure free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 72 5.3 ltps display timing generator the display timing generator generates the timing signals for the internal timing of the source driver and for the panel gate. 5.3.1 1-line period timing the S6D1121 has two drive systems timing output circuits. following preparation of these drive system timing are carried out, a nd a usually different timing signal at the time of a drive a partialness drive is generated. table 5.3.1.1 ltps timing signal information timing circuit 1/2 timing @ 70 hz remark gate circuit clock signal 1 lgclk1b, rgclk1b 43 us gate circuit clock signal 2 lgclk2b, rgclk2b 43 us gate circuit clock signal 3 lgclk3b, rgclk3b 43 us gate circuit clock signal 4 lgclk4b, rgclk4b 43 us gate circuit start pulse signal lgspb, rgspb 43 us multi-plectra switch signal 1 rswb 10 us multi-plectra switch signal 1 gswb 10 us multi-plectra switch signal 1 bswb 10 us the clock set up by the oscillator is being used for the clock of one-line period, and it is generating all timing by using 64 clocks as a base. the one-line period is assigning to 64 clocks and is adjusting frame frequency to within a time of the one line period set up by the oscillator. moreover, the number of clocks of one-line period can be set up by the one-line period clock setting register (r0ah). free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 73 figure 5.3.1.1 1-line driving period (timing circuit 1, timing circuit 2) free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 74 5.3.2 1-line period timing in default value the S6D1121 support the ltps timing on the default value. the default timing is for 70 hz. the line depth of 1h is 43 clocks. figure 5.3.2.1 1-line driving period on defaul t value (timing circuit 1, timing circuit 2) free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 75 5.3.3 1-frame period timing the S6D1121 has two drive systems timing output circuits. following preparation of these drive system timing are carried out, a nd a usually different timing signal at the time of a drive a partialness drive is generated. the timing circuit 2 which is a 2 ph ase gate mode is for the ips panel. also, this mode is not needed on the vcom signal. figure 5.3.3.1 1-frame driving period (timing circuit 2, fld = 00, bp = 3, fp=3, black display) free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 76 figure 5.3.3.2 1-frame driving period (timing circuit 1, fld = 01, fp = 3, bp = 2) notes: source output is black display and line inversion with frame inversion (bc = 1, eor = 1) free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 77 5.3.4 1-frame period timing of 2-line normal display the S6D1121 has 2-line normal function. 2-line normal mode: the source output: 1 ? 2 ? 3 ? ?????? ? 318 ? 319 ? 320 this function needs at least 6 cycles (fp+bp) between odd frame and even frame. this function only supports on the four phase gate mode (timing circuit 1). figure 5.3.4.1 1-frame driving period in 2 line normal (timing circuit 1, fld = 10) free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 78 5.3.5 1-frame period timing of 2-line interlace display the S6D1121 has 2-line interlace function. 2-line interlace mode: the even field source output: 2 ? 4 ? 6 ? 8 ? ?????? ? 318 ? 320 the odd field source output: 1 ? 3 ? 5 ? 7 ? ?????? ? 317 ? 319 there are 4 dummy cycles between odd frame and even frame. this function only supports on the four phase gate mode (timing circuit 1). figure 5.3.5.1 1-frame driving period in 2 line interlace (timing circuit 1, fld = 11) free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 79 5.3.6 1-frame period timing in partial mode the S6D1121 supports 4 phase (timing circuit 1) and 2 phase (timing circuit 2) gate types in the partial display mode. figure 5.3.6.1 1-frame driving period in partial mode (timing circuit 1, fld = 01) free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 80 c figure 5.3.6.2 1-frame driving period in partial mode (timing circuit 2, fld = 00) free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 81 5.4 display function 5.4.1 partial display mode 5.4.1.1 screen-divis ion driving function the S6D1121 is provided with a function that allows sections within the panel to be displayed separately (partial display mode) .the S6D1121 can select and drive two screens at any position with the screen-driving position registers (r42h/ r43h and r44h/r45h). any two screens required for display are selectively driven and hence leads to a reduction in lcd-driving voltage and power consumption. for the 1 st division screen, start line (ss18 to 10) and end line (se18 to 10) are specified by the 1 st screen-driving position register (r42h/r43h). for the 2 nd division screen, start line (ss28 to 20) and end line (se28 to 20) are specified by the 2 nd screen-driving position register (r44h/r45h). the 2 nd screen control is effective when the spt bit is 1. the total count of selection-driving lines for the 1 st and 2 nd screens must correspond to the lcd-driving duty set value. the address of selection-driving lines for the 1 st and 2 nd screens must be specified within the nl5-0 register setting value (lcd-driving duty set value). rm * oct 14th 10:18am line 1 line 7 line 26 line 42 1st screen: 7-raster-row driving non-display area 2nd screen: 17 raster-row driving non-display area ? driving raster-row: nl5-0 = 100111 (320 lines) ? 1st screen setting: ss18-10 = 00h, se18-10 = 06h ? 2nd screen setting: ss28-20 = 19h, se28-20 = 29h, spt = 1 figure 5.4.1.1.1 driving on 2 screens notes: 1. the ?scroll step count register? command is ignored in the partial display mode. 2. the specified partial areas must not directly overlap, and the partial 1 area and partial 2 area must be separated by the at least one line. if the areas overlap, only the partial 1 setting are valid, and partial display is not performed for the partial 2 area. 3. the below table is described about the partial and scroll function operation with fld register. fld partial mode/ scroll mode 00 operation 01 operation 10 operation 11 not operation free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 82 5.4.1.2 restriction on the 1 st /2 nd screen driving position register settings the following restrictions must be satisfied when setting the st art line (ss18 to 10) and end line (se18 to 10) of the 1 st screen driving position register (r42h/r43h) and the start line (ss28 to 20) and end line (se28 to 20) of the 2 nd screen driving position register (r44h/r45h) for the S6D1121. note that incorrect display may occur if the restrictions are not satisfied. table 5.4.1.2.1 restrictions on the 1 st /2 nd screen driving position register setting 1 st screen driving (spt=0) register setting display operation (se18 to 10) ? (ss18 to 10) = nl full screen display normally displays (se18 to 10) to (ss18 to 10) (se18 to 10) ? (ss18 to 10) < nl partial display normally displays (se18 to 10) to (ss18 to 10) white display for all other times (ram data is not related at all) (se18 to 10) ? (ss18 to 10) > nl setting disabled notes: 1. ss18 to 10 se18 to 10 13fh 2. setting se28 to 20 and ss28 to 20 are invalid 2 nd screen driving (spt=1) register setting display operation ((se18 to 10) ? (ss18 to 10)) + ((se28 to 20) ? (ss28-20)) = nl full screen display normally displays (se28 to 10) to (ss18 to 10) ((se18 to 10) ? (ss18 to 10)) + ((se28 to 20) ? (ss28-20)) < nl partial display normally displays (se28 to 10) to (ss18 to 10) white display for all other times (ram data is not related at all) ((se18 to 10) ? (ss18 to 10)) + ((se28 to 20) ? (ss28-20)) > nl setting disabled notes: 1. ss18 to 10 se18 to 10 < ss28 to 20 se28 to 20 13fh 2. (se28 to 20) ? (ss18 to 10) nl the driver output can?t be set for non-display area during the partial display. decision is based on the specification of the p anels. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 83 refer to the following flow to set up the partial display. figure 5.4.1.2.1 partial display set up flow full screen display pt1-0 = 00 set ss/se bits wait (more than 2 frames) pt1-0 = 01 o r pt1-0 = 10 partial display on set ss/se bits full screen display set as need setting flow for full screen driver split screen drive set up flow free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 84 5.4.2 panel vertical scroll mode the S6D1121 has a panel scroll function. any area of the panel can be scrolled by using the scroll area start line register, sc roll area end line register, and scroll step count register. table 5.4.2.1 scroll area start line register (1 st screen area: ss18 ~ ss10, 2 nd screen area: ss28 ~ ss20) ss18 ss17 ss16 ss15 ss14 ss13 ss12 ss11 ss10 start line vertical address 0 0 0 0 0 0 0 0 0 000h 0 0 0 0 0 0 0 0 1 001h 0 0 0 0 0 0 0 1 0 002h 0 0 0 0 0 0 0 1 1 003h 1 0 0 1 1 1 1 0 1 13dh 1 0 0 1 1 1 1 1 0 13eh 1 0 0 1 1 1 1 1 1 13fh table 5.4.2.2 scroll area end line register (1 st screen area: se18 ~ se10, 2 nd screen area: se28 ~ se20) se18 se17 se16 se15 se14 se13 se12 se11 se10 end line vertical address 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 0 1 1 4 1 0 0 1 1 1 1 0 1 318 1 0 0 1 1 1 1 1 0 319 1 0 0 1 1 1 1 1 1 320 table 5.4.2.3 scroll step count register vl8 vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 scroll area line number 0 0 0 0 0 0 0 0 0 0(no scroll) 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 1 1 3 1 0 0 1 1 1 1 0 1 317 1 0 0 1 1 1 1 1 0 318 1 0 0 1 1 1 1 1 1 319 notes: 1. ss18 to 10 se18 to 10 < ss28 to 20 se28 to 20 13fh 2. (se28 to 20) ? (ss18 to 10) nl free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 85 5.4.3 8-color display mode the S6D1121 incorporates 8-color display mode. the used grayscale levels are v0 and v63 and all the other levels (v1~v62) are halted, so that the power consumption is lowered. during the 8-color mode, the gamma micro adjustment register, pkp00-pkp52 and pkn00-pkn52 are invalid. the level power supply (v1-v62) is in off condition during the 8-color mode in order to select v0/v63. gram r 5 r 4 r 3 r 2 r 1 r 0 g 5 g 4 g 3 g 2 g 1 g 0 b 5 b 4 b 3 b 2 b 1 b 0 msb --------------------------------------------------------------------------------------------------------------------------- -------------------lsb binary driver binary driver binary driver r g b lcd 1 msb gvdd avss 1 msb 1 msb figure 5.4.3.1 8-color display control free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 86 figure 5.4.3.2 set up procedure for the 8-color mode free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 87 5.5 display data ram 5.5.1 horizontal / vertical address this ram stores pixel data for display and consists of 4,320 bits (240x18) x 320 bits. any address of this ram can be accessed by specifying an horizontal address and a vertical address. display data ram construction refers to figure 5.5.1. horizontal address circuit: the horizontal address of the display data ram is specified by us ing the horizontal address register (r20h) as shown in figure 5.5.1. the specified horizontal address is increased by one each time display data is written or read. in the horizontal addres s increment mode, the horizontal address is increased up to 0x0ef. if more display data is written or read, the vertical address is increased and the horizontal address returns to 0x000. vertical address circuit: the vertical address of the display data ram is specified by using the vertical address register (r21h) as shown in figure 5.5. 1. the vertical address is increased each by one when one each time display is written or read and horizontal address is increased to last address. when the vertical address has been increased up to 0x13f and the horizontal address up to the final address, if further displa y data is read or written, the horizontal and vertical addresses return to 0x000. figure 5.5.1.1 display data ram construction free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 88 5.5.2 display data addressing address coordinates: as shown in figure 1, display data ram space corresponds to the display area on the panel. the horizontal and vertical addresses make coordinates and their directions make the position of the starting pointing. the direction of the horizontal and vertical addresses is determined by the id0 and id1 commands of the control register (r3h). 5.5.3 display data ram window access mode: with S6D1121, any area of the display ram selected by the mi n horizontal / vertical address registers (r46h and r48h) and max horizontal / vertical address registers (r46h and r47h) can be accessed. first, select the area to be accessed by suing the min horizont al / vertical address registers and max horizontal / vertical address registers. the address scanning setting is also valid in this mode, in the same manner as when data is normally written to the display ram. in addition, data can be written from any address by specifying the horizontal address register (r20h) and vertical address register (r21h). figure 5.5.3.1 window access mode (am = 0) notes : 1. when using the window access mode, the relationship between the start point and end point shown in the table below must be e stablished. 2. if invalid address data is set as the min/max address, operation is not guaranteed. item address relationship horizontal address 0x00 min horizontal address (hsa) max horizontal address (hea) 0xef vertical address 0x000 min vertical address (vsa) max vertical address (vea) 0x13f free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 89 5.5.4 display data ram write and read sequence the below figures show the read and write operation with memory. read operation: in case of 16-/8-bit interface, the lsb of color data will not be read. this function is not available in rgb interface mode. bit assignment rd to db pins reversely operates against write. on the read operation with tri command, this operation is not working. end read more ? index write (20h) yes no index write (21h) ( memory read ) horizontal address write read valid data start rm = 0 vertical address write 18/16-bit bus system end read more ? index write (20h) yes no index write (21h) ( memory read ) horizontal address write read upper word valid data read lower word valid data start rm = 0 vertical address write 9/8-bit bus system index write (22h) read dummy data index write (22h) read dummy data 2 times figure 5.5.4.1 memory data read sequence free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 90 write operation: when the 18-bit rgb interface is in use, 18-bit data is written to ram via pd17-0. this interface is available on the 262,144- colors. when the 16-bit rgb interface is in use, the msb is wri tten to its lsb. this interface is available on the 65,536-color s. end write more ? address is updated by 1 start yes no index write (22h) in the next address? yes no ( memory write ) write data write rm = 0 index write (20h) index write (21h) horizontal address write vertical address write figure 5.5.4.2 memory data write sequence free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 91 5.5.5 window display sequence figure 5.5.5.1 window display sequence free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 92 5.6 mtp (muti time programmable) 5.6.1 mtp calibration mode S6D1121 supports the mtp function. this figure is a operation diagram of mtp. initially, mtp cell is not programmed and has vcomh (6b?00000). when the external reset is applied, mtp mode is on. figure 5.6.1.1 mtp operation diagram 5.6.2 mtp cell structure the mtp has been implemented on the S6D1121. the mtp cell stores the offset volume for vcomh calibration after device has been assembled and calibrated on a lcd module. the mtp_ep and mtp_pp pins used for mtp programming. the mtp block of the S6D1121 consists of one array, which has 7 bits. the msb of 1 bit is used for protection of mtp mode, and 6 bits are used for vcomh calibration (vmh0~vmh5) in the direct gate driving method. on the coupling gate driving method, the 6 bits are vma0 ~ vma5. mprt can be read or be written automatically in this lsi. figure 5.6.2.1 mtp cell structure free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 93 5.6.3 mtp timing figure 5.6.3.1 mtp timing diagram free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 94 5.6.4 mtp sequence flow figure 5.6.4.1 mtp sequence flow note : in mddi mode, it doesn?t work at stb mode. so, it is only active at slp mode in mddi free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 95 5.7 osc S6D1121 can provide r-c oscillation. S6D1121 internal oscillator does not need to be attached to any external resistor. the appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the oscillator frequency control register setting. since r-c osci llation stops during the standby mode, power consumption can be reduced. S6D1121 ex_clk leave this pin open internal clock mode only figure 5.2.12.1 oscillation circuit free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 96 5.8 power supply sequence 5.8.1 external power on / off sequence vdd3 should reach 90% before vci does so, and vice versa, but in this case, vci rising time must be faster than vdd3 rising time within 1ms, and vdd3 rising time must be faster than vci rising time within 1 ms. when regulator cap is 1 f, resetb must be applied after vci & vdd3 have been applied. the applied time gap between vci & vdd3 stable high and resetb is minimum 1ms. as regulator capacitance becomes larger, this time gap must be increased. otherwise function is not guaranteed. figure 5.8.1.1 external power on sequence after vci and vdd3 are stable, normally vci should fall before vdd3 falls, and vdd3 can fall before vci falls. vci falling time must be faster than vdd3 falling time within 1ms, and vdd3 falling time must be faster than vci falling time within 1 ms. figure 5.8.1.2 external power off sequence free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 97 5.8.2 power on / off sequence of direct driving mode with vcom apply the power in a sequence as shown in the following figure. the stable time of the oscillation circuit, step-up circuit, an d operational amplifier depends on the external resistor or capacitance. 10ms or more (stable time of the oscillation circuit ) power supply (vdd, vci, vdd3 on) reset 1ms issues instructions for power supply setting (1) bits for display off . d1-0=00 pon =0 normal display bits for display on : d1 -0 =11 bits for power -supply initial setting : vc 2-0, vrh5-0, vcm5-0, vml5-0,(setting of the source -driver grayscale voltage ) issues instruction for power supply setting (2) bits for power -supply operation start setting : dc 2-0, bits for source - driver operational amplifier operaton -start setting : sap 2-0 bits for step -up circuit 1 operation start pon =1 issues instruction for power supply setting (3) display off bits for display off : d1 -0 =00 instruction for power supply setting (1) bits for source -driver operational amplifier operation -stop setting: sap 2-0 instruction for power supply setting (2) bits for power supply stop setting : aon for operational amplifier , dc2-0 for step-up circuit display off sequence * power supply (vdd ,vci ,vdd3 off) issues instruction for other mode setting display -on sequence * diplay on bits for display on : d1-0=11, gon=1 power -on sequence power -off sequence bits for step -up circuit 2 operation start pon1 =1 bits for amplifier circuit operation start aon =1 80 ms or more (stable time of the step - up operational amplifier ) after vdd is stable set vc = 100 and vr1c = 1100, after reset vc=customer setting 10 ms or more 50 ms or more vr1c=setting, vr 2c=setting figure 5.8.2.1 set up flow of direct driving mode power supply free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 98 5.8.3 direct driving mode instruction setup flow figure 5.8.3.1 direct driving mode instruction set up flow figure 5.8.3.2 direct driving mode instruction setup flow (continued) free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 99 5.8.4 power on / off sequence of coupling driving mode with vcom apply the power in a sequence as shown in the following figure. the stable time of the oscillation circuit, step-up circuit, an d operational amplifier depends on the external resistor or capacitance. 10ms or more (stable time of the oscillation circuit ) power supply (vdd, vci, vdd3 on) reset 300us issues instructions for power supply setting (1) bits for display off . d1-0=00 pon=0 bits for power -supply initial setting : vc 2-0, vrh5-0, vcm5-0, vml5-0,(setting of the source-driver grayscale voltage ) issues instruction for power supply setting (2) bits for power -supply operation start setting : dc2-0, bits for source - driver operational amplifier operaton -start setting : sap2-0 bits for step -up circuit 1 operation start pon =1 issues instruction for power supply setting (3) bits for step -up circuit 2 operation start pon 1=1 bits for amplifier circuit operation start aon =1 after vdd is stable set vc = 100 and vr1c = 1100, after reset display off power supply (vdd,vci ,vdd 3 off) issues instruction for other mode setting diplay on bits for display on : d1-0=11 power -on sequence power -off sequence 20ms or more (stable time of vcomdc charging) prec =1 gon=1 10 ms or more 50 ms or more 80 ms or more (stable time of the step - up operational amplifier ) vc=customer setting vr1c =setting , vr2c=setting figure 5.8.4.1 set up flow of coupling driving mode power supply free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 100 5.8.5 coupling driving mo de instruction setup flow figure 5.8.5.1 coupling driving mode instruction set up flow figure 5.8.5.2 coupling driving mode instruction setup flow (continued) free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 101 5.9 power circuit 5.9.1 power circuit architecture the following figure shows a configuration of the voltage generation circuit for S6D1121. the step-up circuits consist of step- up circuits 1 to 2. step-up circuit1 doubles and triple the voltage supplied to vci1 for avdd level. step-up circuit2 makes 7.5 ~ 16.0v for vgh level (=avdd + vr1 + vr2), and make ?(avdd+vr1) leve l for vgl level. vgl is vglrout regulator power voltage. vr1 block makes 2.0 ~ 5.0v for vgl. vr2 block makes 2.0 ~ 5.0v for vgh level. these step-up circuits generate power supplies avdd, gvdd, vgh, vgl, vglrout, vr1, vr2 and vcom. reference voltages gvdd, vcom, and vglrout for the grayscale voltage are amplified from the voltage adjustment circuit. connect vcom to the tft panel. figure 5.9.1.1 configuration of the internal power-supply circuit note: use the 1uf capacitor. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 102 5.9.2 pattern diagrams for voltage setting the following figure shows a pattern diagram for the voltage setting and an example of waveforms. note : adjust the conditions of avdd-gvdd>0.5v and |vgl|-|vglrout| >0.5 with loads because they are different , depend ing on the display load to be driven. vgh gvdd vcomh vcoml vglrout vcom sn(source output) gn(gate output) vci & vci_ref (2.5 ~ 3.3v) vdd3(1.65 ~ 3.3v) gnd(0v) vgh : 7.5 ~ 16.0v vglrout : -10.5 ~ -5.0v vcoml: 0 ~ 1.0v pon=0 pon=1 pon1= 0 pon1= 1 aon=0 aon=1 t 1 t 2 t 3 vci1:1.75~3.0 v x2 fixed vc[2:0] vref : 2.0v gvdd : 3.0 ~ 5.0v vcomh : 3.52 ~ 5.3v avdd : 4.02 ~ 6.0v vrh vma5-0 vr1c[3:0] vglrc[4:0] amplitude of vcom : 2.3 ~ 5.3v vml5-0 10m s 50m s 40m s vgl : -11.0 ~ -5.5v vdd(1.4 ~ 1.6v) vr1 / vr2 : 2.0 ~ 5.0 v vr2c[3:0] vr1c[3:0] figure 5.9.2.1 pattern diagram and an example of waveforms free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 103 5.10 gamma curve correction 5.10.1 gamma adjustment function the S6D1121 provides the gamma adjustment function to display 262,144 colors simultaneously. the gamma adjustment executed by the micro adjustment register and the amplitude ad justment register determines 14 grayscale levels. furthermore, since the micro-adjustment register and amplitude-adjustment register have the positive polarities and negative polarities, adj ust them to match lcd panel respectively. 64 grayscale control 64 grayscale control 64 grayscale control lcd driver lcd driver lcd driver r g b lcd 6 6 6 v0 v1 v63 grayscale amplifier 64 vrp00 vrp01 vrp02 vrp10 vrp11 vrp12 vrp03 vrp13 vrp14 positive polarity register gram r 5 r 4 r 3 r 2 r 1 r 0 g 5 g 4 g 3 g 2 g 1 g 0 b 5 b 4 b 3 b 2 b 1 b 0 msb --------------------------------------------------------------------------------------------------------------------------- -------------------lsb 12 pkp93 pkp94 pkp95 pkp43 pkp44 pkp45 pkp33 pkp34 pkp35 pkp23 pkp24 pkp25 pkp13 pkp14 pkp15 pkp03 pkp04 pkp05 pkp83 pkp84 pkp85 pkp73 pkp74 pkp75 pkp63 pkp64 pkp65 pkp53 pkp54 pkp55 pkp90 pkp91 pkp92 pkp40 pkp41 pkp42 pkp30 pkp31 pkp32 pkp20 pkp21 pkp22 pkp10 pkp11 pkp12 pkp00 pkp01 pkp02 pkp80 pkp81 pkp82 pkp70 pkp71 pkp72 pkp60 pkp61 pkp62 pkp50 pkp51 pkp52 vrp04 vrn00 vrn01 vrn02 vrn10 vrn11 vrn12 vrn03 vrn13 vrn14 pkn93 pkn94 pkn95 pkn43 pkn44 pkn45 pkn33 pkn34 pkn35 pkn23 pkn24 pkn25 pkn13 pkn14 pkn15 pkn03 pkn04 pkn05 pkn83 pkn84 pkn85 pkn73 pkn74 pkn75 pkn63 pkn64 pkn65 pkn53 pkn54 pkn55 pkn90 pkn91 pkn92 pkn40 pkn41 pkn42 pkn30 pkn31 pkn32 pkn20 pkn21 pkn22 pkn10 pkn11 pkn12 pkn00 pkn01 pkn02 pkn80 pkn81 pkn82 pkn70 pkn71 pkn72 pkn60 pkn61 pkn62 pkn50 pkn51 pkn52 vrn04 negative polarity register pkp113 pkp114 pkp115 pkp103 pkp104 pkp105 pkp110 pkp111 pkp112 pkp100 pkp101 pkp102 pkn113 pkn114 pkn115 pkn103 pkn104 pkn105 pkn110 pkn111 pkn112 pkn100 pkn101 pkn102 figure 5.10.1.1 grayscale control free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 104 5.10.2 structure of grayscale ampilifier the structure of the grayscale amplifier is shown as below. de termine 8-level (vin0-vin11) by the amplitude adjuster and the micro adjustment register. the internal ladder resistance sp lits each level and levels from v0 to v63 are generated. micro adjustment register (10*6 bits) pkp/n0 pkp/n1 pkp/n2 pkpn7 pkp/n8 pkp/n9 reference adjustment register vrp0/vrn0 8to 1 selector gvdd 8to 1 selector 8to 1 selector 8to 1 selector 8to 1 selector vgs ladder resistance grayscale amplifier 8to 1 selector 6 6 6 6 6 6 5 vinp0/vinn0 vinp1/vinn1 vinp2/vinn2 vinp3/vinn3 vinp8/vinn8 vinp9/vinn9 vinp10/vinn10 vinp11/vinn11 v0 v1 v2 v3 v8 v9 v20 v21 v43 v44 v55 v56 v57 v62 v63 5 vrp1/vrn1 amplitude adjustment register figure 5.10.2.1 structure of grayscale amplifier free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 105 5.10.3 gamma adjustment register this block has the registers to set up the grayscale voltage according to the gamma specification of the lcd panel. these registers can be independently set up to positive/negative polariti es and there are 3 types of register groups to adjust gradie nt and amplitude on number of the grayscale, characteristics of the grayscale voltage. (average are common.) the following figure indicates the operation of each adjusting register. figure 5.10.3 operation of adjusting register a) amplitude adjustment resistor the amplitude-adjusting resistor is used to adjust the amplitude of the grayscale voltage. to accomplish the adjustment, it controls the variable resistor (vrp (n)) of the ladder resist or for the grayscale voltage generator located at lower side of th e ladder resistor. (adjust upper side by input gvdd level.) also , there is an independent resistor on the positive/negative polar ities as well as the gradient-adjusting resistor. b) reference adjustment resistor the reference-adjusting resistor is used to adjust the reference of the grayscale voltage. to accomplish the adjustment, it controls the variable resistor (vrp(n)0) of the ladder resistor for the grayscale voltage generator located at upper side of th e ladder resistor. c) micro adjustment resistor the micro adjustment resistor is used to make subtle adjustment of the grayscale voltage level. to accomplish the adjustment, i t controls each reference voltage level by the 64 to 1 selector towards the 64-leveled reference voltage generated from the ladde r resistor. there is also an independent resistor on the positive /negative polarities as well as other adjusting resistors. grayscale number grayscale voltage a) amplitude adjustment grayscale numbe r grayscale voltage c) micro-adjustment grayscale number grayscale voltage b) reference adjustment free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 106 table 5.10.3 gamma correction registers register positive polarity negative polarity set-up contents reference adjustment vrp0[4:0] vrn0[4:0] variable resistor vrp(n)0 ?sets grayscale 0 pkp0[5:0] pkn0[5:0] the voltage of grayscale number 1 is selected by the 8 to 1 selector pkp1[5:0] pkn1[5:0] the voltage of grayscale number 5 is selected by the 8 to 1 selector pkp2[5:0] pkn2[5:0] the voltage of grayscale number 6 is selected by the 8 to 1 selector pkp3[5:0] pkn3[5:0] the voltage of grayscale number 8 is selected by the 8 to 1 selector pkp4[5:0] pkn4[5:0] the voltage of grayscale number 16 is selected by the 8 to 1 selector pkp5[5:0] pkn5[5:0] the voltage of grayscale number 23 is selected by the 8 to 1 selector pkp6[5:0] pkn6[5:0] the voltage of grayscale number 40 is selected by the 8 to 1 selector pkp7[5:0] pkn7[5:0] the voltage of grayscale number 47 is selected by the 8 to 1 selector pkp8[5:0] pkn8[5:0] the voltage of grayscale number 55 is selected by the 8 to 1 selector pkp9[5:0] pkn9[5:0] the voltage of grayscale number 57 is selected by the 8 to 1 selector pkp10[5:0] pkn10[5:0] the voltage of grayscale number 58 is selected by the 8 to 1 selector micro-adjustment pkp11[5:0] pkn11[5:0] the voltage of grayscale number 62 is selected by the 8 to 1 selector amplitude adjustment vrp1[4:0] vrn1[4:0] variable resistor vrp(n)1 ?sets grayscale 63 free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 107 5.10.4 ladder resistor/8 to 1 selector this block outputs the reference voltage of the grayscale voltage. there are two ladder resistors including the variable resist or and the 8 to 1 selector which selects the voltage generated by t he ladder resistance voltage. the variable resistors and 8 to 1 resistors are controlled by the gamma resistor. also, there are pins that connect to the external volume resistor. in addition, it allows compensating the dispersion of length from one panel to another. 5.10.4.1 variable resistor variable resistors are used for the gradient for the amplitude adjustment and reference adjustment (vrp (n)). the resistance value is set by the gradient adjusting resistor and the amplitude adjustment resistor as shown below. table 5.10.4.1.1 reference adjustment register value vrp(n)0[4:0] resistance value vrp(n)0 00000 0r 00001 1r 00010 2r . . . . . . 11101 29r 11110 30r 11111 31r table 5.10.4.1.2 amplitude adjustment register value vrp(n)1[4:0] resistance value vrp(n)1 00000 0r 00001 1r 00010 2r . . . . . . 11101 29r 11110 30r 11111 31r free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 108 5.10.4.2 the 64 to 1 selector in the 64 to 1 selector, the voltage level must be selected given by the ladder resistance and the micro-adjusting register. th e output voltage is given by the six types of the reference voltage, the vin1 to vin12. following figure explains the relationship between the micro-adjusting register and the selected voltage. table 5.10.4.2.1 relationship table between micro-adjustment register and selected voltage register pkp(n) [5:0] vinp(n) 1 vinp(n) 2 vinp(n) 3 vinp(n) 4 vinp(n) 5 vinp(n) 6 vinp(n) 7 vinp(n) 8 vinp(n) 9 vinp(n) 10 vinp(n) 11 vinp(n) 12 000000 1 9 9 23 34 46 66 73 80 88 88 96 000001 2 10 10 24 35 47 67 74 81 89 89 97 000010 3 11 11 25 36 48 68 75 82 90 90 98 000011 4 12 12 26 37 49 69 76 83 91 91 99 000100 5 13 13 27 38 50 70 77 84 92 92 100 000101 6 14 14 28 39 51 71 78 85 93 93 101 000110 7 15 15 29 40 52 72 79 86 94 94 102 000111 8 16 16 30 41 53 73 80 87 95 95 103 001000 9 17 17 31 42 54 74 81 88 96 96 104 001001 10 18 18 32 43 55 75 82 89 97 97 105 001010 11 19 19 33 44 56 76 83 90 98 98 106 001011 12 20 20 34 45 57 77 84 91 99 99 107 001100 13 21 21 35 46 58 78 85 92 100 100 108 001101 14 22 22 36 47 59 79 86 93 101 101 109 001110 15 23 23 37 48 60 80 87 94 102 102 110 001111 16 24 24 38 49 61 81 88 95 103 103 111 010000 17 25 25 39 50 62 82 89 96 104 104 112 010001 18 26 26 40 51 63 83 90 97 105 105 113 010010 19 27 27 41 52 64 84 91 98 106 106 114 010011 20 28 28 42 53 65 85 92 99 107 107 115 010100 21 29 29 43 54 66 86 93 100 108 108 116 010101 22 30 30 44 55 67 87 94 101 109 109 117 010110 23 31 31 45 56 68 88 95 102 110 110 118 010111 24 32 32 46 57 69 89 96 103 111 111 119 011000 25 33 33 47 58 70 90 97 104 112 112 120 011001 26 34 34 48 59 71 91 98 105 113 113 121 011010 27 35 35 49 60 72 92 99 106 114 114 122 011011 28 36 36 50 61 73 93 100 107 115 115 123 011100 29 37 37 51 62 74 94 101 108 116 116 124 011101 30 38 38 52 63 75 95 102 109 117 117 125 011110 31 39 39 53 64 76 96 103 110 118 118 126 011111 32 40 40 54 65 77 97 104 111 119 119 127 100000 33 41 41 55 66 78 98 105 112 120 120 128 100001 34 42 42 56 67 79 99 106 113 121 121 129 100010 35 43 43 57 68 80 100 107 114 122 122 130 100011 36 44 44 58 69 81 101 108 115 123 123 131 100100 37 45 45 59 70 82 102 109 116 124 124 132 100101 38 46 46 60 71 83 103 110 117 125 125 133 100110 39 47 47 61 72 84 104 111 118 126 126 134 100111 40 48 48 62 73 85 105 112 119 127 127 135 101000 41 49 49 63 74 86 106 113 120 128 128 136 101001 42 50 50 64 75 87 107 114 121 129 129 137 free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 109 101010 43 51 51 65 76 88 108 115 122 130 130 138 101011 44 52 52 66 77 89 109 116 123 131 131 139 101100 45 53 53 67 78 90 110 117 124 132 132 140 101101 46 54 54 68 79 91 111 118 125 133 133 141 101110 47 55 55 69 80 92 112 119 126 134 134 142 101111 48 56 56 70 81 93 113 120 127 135 135 143 110000 49 57 57 71 82 94 114 121 128 136 136 144 110001 50 58 58 72 83 95 115 122 129 137 137 145 110010 51 59 59 73 84 96 116 123 130 138 138 146 110011 52 60 60 74 85 97 117 124 131 139 139 147 110100 53 61 61 75 86 98 118 125 132 140 140 148 110101 54 62 62 76 87 99 119 126 133 141 141 149 110110 55 63 63 77 88 100 120 127 134 142 142 150 110111 56 64 64 78 89 101 121 128 135 143 143 151 111000 57 65 65 79 90 102 122 129 136 144 144 152 111001 58 66 66 80 91 103 123 130 137 145 145 153 111010 59 67 67 81 92 104 124 131 138 146 146 154 111011 60 68 68 82 93 105 125 132 139 147 147 155 111100 61 69 69 83 94 106 126 133 140 148 148 156 111101 62 70 70 84 95 107 127 134 141 149 149 157 111110 63 71 71 85 96 108 128 135 142 150 150 158 111111 64 72 72 86 97 109 129 136 143 151 151 159 free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 110 table 5.10.4.2.2 gamma adjusting voltage formula (positive polarity) grayscale voltage formula grayscale voltage formula v0 vinn0 v32 v40+(v23-v40)*8/17.1 v1 vinn1 v33 v40+(v23-v40)*7/17.1 v2 v5+(v1-v5)*(9/13) v34 v40+(v23-v40)*6/17.1 v3 v5+(v1-v5)*(6/13) v35 v40+(v23-v40)*5/17.1 v4 v5+(v1-v5)*(2.5/13)) v36 v40+(v23-v40)*4/17.1 v5 vinn2 v37 v40+(v23-v40)*3/17.1 v6 vinn3 v38 v40+(v23-v40)*217.1 v7 v8+(v6-v8)*1/2 v39 v40+(v23-v40)*1/17.1 v8 vinn4 v40 vinn7 v9 v16+(v8-v16)*7.6/8.9 v41 v47+(v40-v47)*6.4/7.4 v10 v16+(v8-v16)*6.3/8.9 v42 v47+(v40-v47)*5.4/7.4 v11 v16+(v8-v16)*5/8.9 v43 v47+(v40-v47)*4.4/7.4 v12 v16+(v8-v16)*4/8.9 v44 v47+(v40-v47)*3.4/7.4 v13 v16+(v8-v16)*3/8.9 v45 v47+(v40-v47)*2.4/7.4 v14 v16+(v8-v16)*2/8.9 v46 v47+(v40-v47)*1.2/7.4 v15 v16+(v8-v16)*1/8.9 v47 vinn8 v16 vinn5 v48 v55+(v47-v55)*9.7/10.7 v17 v23+(v16-v23)*6.2/7.4 v49 v55+(v47-v55)*8.6/10.7 v18 v23+(v16-v23)*5/7.4 v50 v55+(v47-v55)*7.4/10.7 v19 v23+(v16-v23)*4/7.4 v51 v55+(v47-v55)*6.1/10.7 v20 v23+(v16-v23)*3/7.4 v52 v55+(v47-v55)*4.7/10.7 v21 v23+(v16-v23)*2/7.4 v53 v55+(v47-v55)*3.2/10.7 v22 v23+(v16-v23)*1/7.4 v54 v55+(v47-v55)*1.6/10.7 v23 vinn6 v55 vinn9 v24 v40+(v23-v40)*16.1/17.1 v56 v57+(v55-v57)*1/2 v25 v40+(v23-v40)*15/17.1 v57 vinn10 v26 v40+(v23-v40)*14/17.1 v58 vinn11 v27 v40+(v23-v40)*13/17.1 v59 v62+(v58-v62)*10.5/13 v28 v40+(v23-v40)*12/17.1 v60 v62+(v58-v62)*7.5/13 v29 v40+(v23-v40)*11/17.1 v61 v62+(v58-v62)*4/13 v30 v40+(v23-v40)*10/17.1 v62 vinn12 v31 v40+(v23-v40)*9/17.1 v63 vinn13 free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 111 table 5.10.4.2.3 gamma adjusting voltage formula (negative polarity) grayscale voltage formula grayscale voltage formula v0 vinp0 v32 v40+(v23-v40)*8/17.1 v1 vinp1 v33 v40+(v23-v40)*7/17.1 v2 v5+(v1-v5)*(9/13) v34 v40+(v23-v40)*6/17.1 v3 v5+(v1-v5)*(6/13) v35 v40+(v23-v40)*5/17.1 v4 v5+(v1-v5)*(2.5/13)) v36 v40+(v23-v40)*4/17.1 v5 vinp2 v37 v40+(v23-v40)*3/17.1 v6 vinp3 v38 v40+(v23-v40)*217.1 v7 v8+(v6-v8)*1/2 v39 v40+(v23-v40)*1/17.1 v8 vinp4 v40 vinp7 v9 v16+(v8-v16)*7.6/8.9 v41 v47+(v40-v47)*6.4/7.4 v10 v16+(v8-v16)*6.3/8.9 v42 v47+(v40-v47)*5.4/7.4 v11 v16+(v8-v16)*5/8.9 v43 v47+(v40-v47)*4.4/7.4 v12 v16+(v8-v16)*4/8.9 v44 v47+(v40-v47)*3.4/7.4 v13 v16+(v8-v16)*3/8.9 v45 v47+(v40-v47)*2.4/7.4 v14 v16+(v8-v16)*2/8.9 v46 v47+(v40-v47)*1.2/7.4 v15 v16+(v8-v16)*1/8.9 v47 vinp8 v16 vinp5 v48 v55+(v47-v55)*9.7/10.7 v17 v23+(v16-v23)*6.2/7.4 v49 v55+(v47-v55)*8.6/10.7 v18 v23+(v16-v23)*5/7.4 v50 v55+(v47-v55)*7.4/10.7 v19 v23+(v16-v23)*4/7.4 v51 v55+(v47-v55)*6.1/10.7 v20 v23+(v16-v23)*3/7.4 v52 v55+(v47-v55)*4.7/10.7 v21 v23+(v16-v23)*2/7.4 v53 v55+(v47-v55)*3.2/10.7 v22 v23+(v16-v23)*1/7.4 v54 v55+(v47-v55)*1.6/10.7 v23 vinp6 v55 vinp9 v24 v40+(v23-v40)*16.1/17.1 v56 v57+(v55-v57)*1/2 v25 v40+(v23-v40)*15/17.1 v57 vinp10 v26 v40+(v23-v40)*14/17.1 v58 vinp11 v27 v40+(v23-v40)*13/17.1 v59 v62+(v58-v62)*10.5/13 v28 v40+(v23-v40)*12/17.1 v60 v62+(v58-v62)*7.5/13 v29 v40+(v23-v40)*11/17.1 v61 v62+(v58-v62)*4/13 v30 v40+(v23-v40)*10/17.1 v62 vinp12 v31 v40+(v23-v40)*9/17.1 v63 vinp13 free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 112 000000 111111 v63 v0 output level negative polarity positive polarity ram data (common charactersics to rgb) figure 5.10.4.2.1 relationship between ram data and output voltage positive polarity negative polarity sn vcom figure 5.10.4.2.2 relationship between source output and vcom free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 113 6. reset if the /reset input becomes low (?0?), the internal timing generator is initialized. the reset command will also initialize eac h register to its default value. these default values are listed in the table below (register number is an estimate. understand t hat there is a case where it changes later). register reset command default value driver output control(r01h) r01 o 0027h lcd-driving-waveform control (r02h) r02 o 0003h entry mode(r03h) r03 o 0003h oscillator control (r04h) r04 o 2801h display control (r07h) r07 o 0000h blank period control 1 (r08h) r08 o 0404h frame cycle control 1 (r0ah) r0a o 000bh frame cycle control (r0bh) r0b o 0003h external interface control(r0ch) r0c o 0000h power control 1 (r10h) r10 o 0000h power control 2 (r11h) r11 o 0004h power control 3 (r12h) r12 o 0033h power control 4 (r13h) r13 o 0c00h power control 5 (r14h) r14 o 0000h power control 6 (r15h) r15 o 0000h power control 7 (r16h) r16 o 0006h ram address set 1 (r20h) r20 o 0000h ram address set 2 (r21h) r21 o 0000h gamma control 1 (r30h) r30 o 0000h gamma control 2 (r31h) r31 o 0000h gamma control 3 (r32h) r32 o 0000h gamma control 4 (r33h) r33 o 0000h gamma control 5 (r34h) r34 o 0000h gamma control 6 (r35h) r35 o 0000h gamma control 7 (r36h) r36 o 0000h gamma control 8 (r37h) r37 o 0000h gamma control 9 (r38h) r38 o 0000h gamma control 10 (r39h) r39 o 0000h gamma control 11 (r3ah) r3a o 0000h gamma control 12 (r3bh) r3b o 0000h gamma control 13 (r3ch) r3c o 0000h gamma control 14 (r3dh) r3d o 0000h vertical scroll control (r41h) r41 o 0000h 1 st screen driving position (r42h) r42 o 013fh 1 st screen driving position (r43h) r43 o 0000h 2 nd screen driving position (r44h) r44 o 013fh 2 nd screen driving position (r45h) r45 o 0000h horizontal window address (r46h) r46 o ef00h vertical window address (r47h) r47 o 013fh vertical window address (r48h) r48 o 0000h mddi wake up control (r50h) r50 o 0000h mddi link wake-up start position (r51h) r51 o 0000h sub panel control 1 (r52h) r52 o 000ah sub panel control 2 (r53h) r53 o 007ah sub panel control 3 (r54h) r54 o 0022h gpio value(r55h) r55 o 0000h gpio in/output control(r56h) r56 o 0000h gpio clear(r57h) r57 o 0000h gpio interrupt enable(r58h) r58 o 0000h gpio polarity selection (r59h) r59 o 03ffh free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 114 mtp init(r60h) r60 o 0005h mtp vcomh read(r61h) r61 o 0000h set mtp test key(r62h) r62 o 0000h timing of signal from goe (r70h) r70 o 010bh gate start pulse delay timing (r71h) r71 o 0000h red output start timing (r72h) r72 o 0001h green output start timing (r73h) r73 o 0003h blue output start timing (r74h) r74 o 0003h rsw timing (r75h) r75 o 0102h gsw timing (r76h) r76 o 0102h bsw timing (r77h) r77 o 0102h vcom output control (r78h) r78 o 0000h panel signal control 1 (r79h) r79 o 0000h panel signal control2 (r7ah) r7a o 0000h gate1, 2 switching control(r97h) r97 o 0000h note: o: default value set, x: default value not set free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 115 7. commands 7.1 instruction table reg. no r/w rs ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 register name / description ir 0 0 0 0 0 0 0 0 0 0 id7 id6 id5 id4 id3 id2 id1 id0 index / sets the index register value sr 1 0 0 0 0 0 0 0 0 l8 l7 l6 l5 l4 l3 l2 l1 l0 status read / reads the internal status of the S6D1121 0 1 * * * * * * * * * * * * * * * * production code r00h 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 production code read / production code r01h 0 1 vspl hspl dpl epl 0 0 0 ss 0 0 nl5 nl4 nl3 nl2 nl1 nl0 driver output control(r01h) / vspl: set polarity of vsync pin. hspl: set polarity of hsync pin. dpl: set polarity of dotclk pin. epl: set polarity of enable pin ss: source driver shift direction nl5-0: number of driving lines r02h 0 1 0 0 0 0 0 0 0 gud 0 sinv fld1 fld0 0 0 b/c eor lcd-driving-waveform control (r02h)/ gud: set the gate direction sinv: inverts the polarity of source output fld1-0: number of interlaced field b/c: lcd drive ac waveform eor: exclusive or-ing the ac waveform r03h 0 1 tri dfm 0 bgr 0 0 0 0 0 0 0 0 am 0 i/d1 i/d0 entry mode(r03h) / tri : 8-bit interface mode dfm: defines color depth for the ic bgr: rgb swap control am: set the automatic update method of the ac i/d1-0: address counter increment / decrement control r04h 0 1 0 0 radj 5 radj 4 radj 3 radj 2 radj 1 radj 0 0 0 0 0 0 0 0 osc_o n oscillator control (r04h)/ radj5-0 : osc freq select osc_on : start oscillation r07h 0 1 pt1 pt0 vle2 vle1 0 0 0 spt 0 gon cl rev 0 0 d1 d0 display control (r07h) / pt1-0: non-display area source output control vle2-1: 1 st /2 nd partial vertical scroll spt: 1 st /2 nd partial display enable gon: gate on/off control cl: 8-color display mode enable rev: display area inversion drive d1-0: source output control r08h 0 1 fmp1 fmp0 0 0 fp3 fp2 fp1 fp0 0 0 0 0 bp3 bp2 bp1 bp0 blank period control 1 (r08h)/ fmp1-0: set the output timing of frame cycle signal fp3-0: front porch setting bp3-0: back porch setting r0ah 0 1 0 0 0 0 ecs3 ecs2 ecs1 ecs0 0 0 0 rtn4 rtn3 rtn2 rtn1 rtn0 frame cycle control 1 (r0ah)/ ecs3-0: vci recycling period setting. rtn5-0: set the 1-h period r0bh 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 dcr2 dcr1 dcr0 frame cycle control (r0bh)/ dcr2-0:set clock cycle for step-up circuit. r0ch 0 1 0 0 0 0 0 0 0 0 0 rm dm1 dm0 0 0 rim1 rim0 external interface control(r0ch) / rm: specify the interface for ram access dm1-0: specify display operation mode rim1-0: specify rgb-i/f mode r10h 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slp stb power control 1 (r10h) / slp: sleep mode control stb: standby mode control r11h 0 1 0 0 vrh5 vrh4 vrh3 vrh2 vrh1 vrh0 0 vci1_ off 0 0 0 0 vc1 vc0 power control 2 (r11h)/ vrh5-0:set gvdd voltage vci1_off:control vci1 voltage generation vc1-0:set vci1 voltage r12h 0 1 0 0 0 0 0 0 0 0 0 sap2 sap1 sap0 0 dc2 dc1 dc0 power control 3 (r12h) / sap2-0:adjust fixed current dc2-0:adjust the frequency r13h 0 1 vr2c 3 vr2c 2 vr2c 1 vr2c 0 vr1c 3 vr1c 2 vr1c 1 vr1c 0 vglrc 4 vglr c3 vglr c2 vglr c1 vglr c0 pon pon1 aon power control 4 (r13h)/ vr2c4~0: set the vr2 voltage vr1c4~0: set the vr1 voltage vglrc4~0:set the vglr voltage pon: booster circuit control pon1: booster circuit control aon: operation start bit for the amplifier. r14h 0 1 0 0 vcm5 vcm4 vcm3 vcm2 vcm1 vcm0 0 0 vml5 vml4 vml3 vml2 vml1 vml0 power control 5 (r14h)/ vcm5-0:set the vcomh voltage vml4-0:set the amplitude of vcom voltage r15h 0 1 vcm r 0 vma5 vma4 vma3 vma2 vma1 vma0 0 0 vmh5 vmh4 vmh3 vmh2 vmh1 vmh0 power control 6 (r15h)/ vcmr: vcomh control by vcomr pin vma5-0:set the vcomh voltage (coupling) vmh5-0:set the vcomh voltage (direct) r16h 0 1 0 0 0 0 0 0 0 0 vcom_ off 0 0 0 0 prec coms coma power control 7 (r17h)/ vcom_off: control on/off the vcom, vcomprec and vcomdc. prec: control the pre-charge for coupling vcom driving method coms: selection the vcom driving method coma: setup vcoml voltage r20h 0 1 0 0 0 0 0 0 0 0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r21h 0 1 0 0 0 0 0 0 0 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write data to gram (r20h)/ (r21h) ad16- 0:input data for gram free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 116 0 1 wd17-0 : pin assignment varies according to the interface method write data to gram (r22h)/ wd17-0:input data for gram r22h 1 1 rd17-0 : pin assignment varies according to the interface method read data from gram (r22h)/ rd17-0:read data from gram r30h 0 1 0 0 pkp1[5:0] 0 0 pkp0[5:0] gamma control 1 (r30h)/ adjust gamma voltage r31h 0 1 0 0 pkp3[5:0] 0 0 pkp2[5:0] gamma control 2 (r31h)/ adjust gamma voltage r32h 0 1 0 0 pkp5[5:0] 0 0 pkp4[5:0] gamma control 3 (r32h)/ adjust gamma voltage r33h 0 1 0 0 pkp7[5:0] 0 0 pkp6[5:0] gamma control 4 (r33h)/ adjust gamma voltage r34h 0 1 0 0 pkp9[5:0] 0 0 pkp8[5:0] gamma control 5 (r34h)/ adjust gamma voltage r35h 0 1 0 0 pkp11[5:0] 0 0 pkp10[5:0] gamma control 6 (r35h)/ adjust gamma voltage r36h 0 1 0 0 pkn1[5:0] 0 0 pkn0[5:0] gamma control 7 (r36h)/ adjust gamma voltage r37h 0 1 0 0 pkn3[5:0] 0- 0 pkn2[5:0] gamma control 8 (r37h)/ adjust gamma voltage r38h 0 1 0 0 prn5[5:0] 0 0 prn4[5:0] gamma control 9 (r38h)/ adjust gamma voltage r39h 0 1 0 0 pkn7[5:0] 0- 0 pkn6[5:0] gamma control 10 (r39h)/ adjust gamma voltage r3ah 0 1 0 0 prn9[5:0] 0 0 prn8[5:0] gamma control 11 (r3ah)/ adjust gamma voltage r3bh 0 1 0 0 prn11[5:0] 0 0 prn10[5:0] gamma control 12 (r3bh)/ adjust gamma voltage r3ch 0 1 0 0 0 vrp1[4:0] 0 0 0 vrp0[4:0] gamma control 13 (r3ch)/ adjust amplitude voltage r3dh 0 1 0 0 0 vrn1[4:0] 0 0 0 vrn0[4:0] gamma control 14 (r3dh)/ adjust amplitude voltage r41h 0 1 0 0 0 0 0 0 0 vl8 vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 vertical scroll control (r41h)/ vl8-0: r42h 0 1 0 0 0 0 0 0 0 se18 se17 se16 se15 se14 se13 se12 se11 se10 r43h 0 1 0 0 0 0 0 0 0 ss18 ss17 ss16 ss15 ss14 ss13 ss12 ss11 ss10 1 st screen driving position (r42h, r43h) se18-10: 1 st screen end position ss18-10: 1 st screen start position r44h 0 1 0 0 0 0 0 0 0 se28 se27 se26 se25 se24 se23 se22 se21 se20 r45h 0 1 0 0 0 0 0 0 0 ss28 ss27 ss26 ss25 ss24 ss23 ss22 ss21 ss20 2 nd screen driving position (r44h, r45h) se28-20: 2 nd screen end position ss28-20: 2 nd screen start position r46h 0 1 hea7 hea6 hea5 hea4 hea3 hea2 hea1 hea0 hsa7 hsa6 hsa5 hsa4 hsa3 hsa2 hsa1 hsa0 horizontal window address (r46h) hsa7-0: horizontal window address start position hea7-0: horizontal window address end position r47h 0 1 0 0 0 0 0 0 0 vea8 vea7 vea6 vea5 vea4 vea3 vea2 vea1 vea0 r48h 0 1 0 0 0 0 0 0 vsa8 vsa7 vsa6 vsa5 vsa4 vsa3 vsa2 vsa1 vsa0 vertical window address (r47h, r48h) vea8-0: vertical window address end position vsa8-0: vertical window address start position r50h 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wak e_en mddi wake up control (r50h)/ when vwake_en = 1, client initiated wakeup is enabled. r51h 0 1 wkl7 wkl6 wkl5 wkl4 wkl3 wkl2 wkl1 wkl0 0 0 0 0 wkf3 wkf2 wkf1 wkf0 mddi link wake-up start position (r51h)/ wkf : the frame that data is written wkl : the line that data is written r52h 0 1 0 0 0 0 0 0 0 0 0 0 0 0 mode_sel[1: 0] sub_im[1:0] sub panel control 1 (r52h)/ sub_im[1-0] : bus width mode_sel [1:0]: stn, mpu interface r53h 0 1 0 0 0 0 0 0 0 0 sub_sel sub panel control 2 (r53h)/ sub panel selection index sub_sel: select main/sub panel r54h 0 1 0 0 0 0 0 0 0 0 sub_wr sub panel control 3 (r54h)/ sub_wr: gram write data sub frame r55h 0 0 0 0 0 0 gpio_data[9:0] gpio value(r55h) gpio_data 9-0 r56h 0 0 0 0 0 0 gpio_con[9:0] gpio in/output control(r56h) gpio_con 9-0 r57h 0 0 0 0 0 0 gpio_clr[9:0] gpio clear(r57h) gpio_clr 9-0 r58h 0 0 0 0 0 0 gpio_en[9:0] gpio interrupt enable(r58h) gpio_en 9-0 r59h 0 0 0 0 0 0 gpio_pol[9:0] gpio polarity selection (r59h) gpio_pol 9-0 r60h 0 1 0 0 0 0 0 0 0 0 0 0 0 0 mtp_ load mtp_ wrb mtp_ sel mtp_ erb mtp init(r60h) mtp_load: mtp data load. mtp_wrb : mtp program enable signal mtp_sel : vcomh selection mtp_erb: mtp initial mode control r61h 0 1 0 0 0 0 0 0 0 0 0 mtp_d[6:0] mtp vcomh read(r61h) dummy: r62h 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 set mtp test key(r62h) 8ch r70h 0 1 0 0 0 0 0 0 gost[1:0] 0 0 0 goed[4:0] timing of signal from goe (r70h)/ gost[1:0] : start timing goed[4:0] : end timing free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 117 r71h 0 1 0 0 0 0 0 0 0 0 0 0 0 0 gsp_dly[3:0] gate start pulse delay timing (r71h)/ gsp_dly3-0 : gate start pulse delay r72h 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 r_stp[2:0] red output start timing (r72h)/ r_stp[2:0] : red output start timing r73h 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 g_stp[2:0] green output start timing (r73h)/ g_stp[2:0] : green output start timing r74h 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 b_stp[2:0] blue output start timing (r74h)/ b_stp[2:0] : blue output start timing r75h 0 1 0 0 0 0 0 0 m_rstp[1:0] 0 0 0 0 0 m_rpw[2:0] rsw timing (r75h)/ m_rstp1-0 : start timing of rsw m_rpw2-0 : pulse width timing of rsw r76h 0 1 0 0 0 0 0 0 m_gstp[1:0] 0 0 0 0 0 m_gpw[2:0] gsw timing (r76h)/ m_gstp1-0 : start timing of gsw m_gpw2-0 : pulse width timing of gsw r77h 0 1 0 0 0 0 0 0 m_bstp[1:0] 0 0 0 0 0 m_bpw[2:0] bsw timing (r77h)/ m_bstp-0 : start timing of bsw m_bpw2-0 : pulse width timing of bsw r78h 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vmchg[1:0] vcom output control (r78h) vmchg1-0 : starting time of vcom output r79h 0 1 0 0 lgsp _off lgcl k4_o ff lgcl k3_o ff lgcl k2_o ff lgcl k1_o ff 0 rgsp_ off rgcl k4_o ff rgcl k3_o ff rgcl k2_o ff rgcl k1_o ff r_of f g_of f b_of f panel signal control 1 (r79h)/ lgsp_off : gsp output control lgclk4_off : gclk4 output control lgclk3_off : gclk3 output control lgclk2_off : gclk2 output control lgclk1_off : gclk1 output control rgsp_off : gsp output control rgclk4_off : gclk4 output control rgclk3_off : gclk3 output control rgclk2_off : gclk2 output control rgclk1_off : gclk1 output control r_off : rsw output control g_off : gsw output control b_off : bsw output control r7ah 0 1 0 0 lgsp _pol lgcl k4_p ol lgcl k3_p ol lgcl k2_p ol lgcl k1_p ol 0 rgsp_ pol rgcl k4_p ol rgcl k3_p ol rgcl k2_p ol rgcl k1_p ol r_po l g_po l b_po l panel signal control2 (r7ah)/ lgsp_pol : gsp polarity control lgclk4_pol : gclk4 polarity control lgclk3_pol : gclk3 polarity control lgclk2_pol : gclk2 polarity control lgclk1_pol : gclk1 polarity control rgsp_pol : gsp polarity control rgclk4_pol : gclk4 polarity control rgclk3_pol : gclk3 polarity control rgclk2_pol : gclk2 polarity control rgclk1_pol : gclk1 polarity control r_pol : rsw polarity control g_pol : gsw polarity control b_pol : bsw polarity control r90h 0 1 test command1 don?t use this command r91h ~ r96h 0 1 test command2 don?t use this command r97h 0 1 0 0 0 0 0 0 0 0 chng 0 0 0 0 0 0 0 chng : swap gclk1 and gclk2 free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 118 7.2 instruction description production code (r00h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 * * * * * * * * * * * * * * * * r 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 default 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 if this register is read forcibly, *1121h is read. driver output control (r01h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 vsp l hsp l dpl epl 0 0 0 ss 0 0 nl5 nl4 nl3 nl2 nl1 nl0 default 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 vspl: reverses the polarity of the vsync signal. vspl= ?0?: vsync is low active. vspl= ?1?: vsync is high active. hspl: reverses the polarity of the hsync signal. hspl= ?0?: hsync is low active. hspl= ?1?: hsync is high active. dpl: reverses the polarity of the dotclk signal. dpl= ?0?: display data is fetched on the rising edge of dotclk. dpl= ?1?: display data is fetched on the falling edge of dotclk. epl: set the polarity of enable pin while using rgb interface. epl = ?0?: enable = ?low? / write data of pd17-0 enable = ?high? / don?t write data of pd17-0 epl = ?1?: enable = ?high? / write data of pd17-0 enable = ?low? / don?t write data of pd17-0 ss: selects the output shift direction of the source driver. when ss = 0, s1 shifts to s240. when ss = 1, s240 shifts to s1. in addition, ss and bgr bits should be specified in case of any change in the rgb order. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 119 nl5?0: specify the number of raster-rows to be driven. the number of raster-row can be adjusted in units of eight. the address mapping of gram is independent of this setting. the set value should be higher than the panel size. table 7.2.1 nl bit and driver duty nl5 nl4 nl3 nl2 nl1 nl0 display size lcd raster rows gate- lines used 0 0 0 0 0 0 setting disabled setting disabled setting disabled 0 0 0 0 0 1 240rgb x 16 16 g1 to g16 0 0 0 0 1 0 240rgb x 24 24 g1 to g24 0 0 0 0 1 1 240rgb x 32 32 g1 to g32 0 0 0 1 0 0 240rgb x 40 40 g1 to g40 0 0 0 1 0 1 240rgb x 48 48 g1 to g48 0 0 0 1 1 0 240rgb x 56 56 g1 to g56 0 0 0 1 1 1 240rgb x 64 64 g1 to g64 0 0 1 0 0 0 240rgb x 72 72 g1 to g72 0 0 1 0 0 1 240rgb x 80 80 g1 to g80 0 0 1 0 1 0 240rgb x 88 88 g1 to g88 0 0 1 0 1 1 240rgb x 96 96 g1 to g96 0 0 1 1 0 0 240rgb x 104 104 g1 to g104 0 0 1 1 0 1 240rgb x 112 112 g1 to g112 0 0 1 1 1 0 240rgb x 120 120 g1 to g120 0 0 1 1 1 1 240rgb x 128 128 g1 to g128 0 1 0 0 0 0 240rgb x 136 136 g1 to g136 0 1 0 0 0 1 240rgb x 144 144 g1 to g144 0 1 0 0 1 0 240rgb x 152 152 g1 to g152 0 1 0 0 1 1 240rgb x 160 160 g1 to g160 0 1 0 1 0 0 240rgb x 168 168 g1 to g168 0 1 0 1 0 1 240rgb x 176 176 g1 to g176 0 1 0 1 1 0 240rgb x 184 184 g1 to g184 0 1 0 1 1 1 240rgb x 192 192 g1 to g192 0 1 1 0 0 0 240rgb x 200 200 g1 to g200 0 1 1 0 0 1 240rgb x 208 208 g1 to g208 0 1 1 0 1 0 240rgb x 216 216 g1 to g216 0 1 1 0 1 1 240rgb x 224 224 g1 to g224 0 1 1 1 0 0 240rgb x 232 232 g1 to g232 0 1 1 1 0 1 240rgb x 240 240 g1 to g240 0 1 1 1 1 0 240rgb x 248 248 g1 to g248 0 1 1 1 1 1 240rgb x 256 256 g1 to g256 1 0 0 0 0 0 240rgb x 264 264 g1 to g264 1 0 0 0 0 1 240rgb x 272 272 g1 to g272 1 0 0 0 1 0 240rgb x 280 280 g1 to g280 1 0 0 0 1 1 240rgb x 288 288 g1 to g288 1 0 0 1 0 0 240rgb x 296 296 g1 to g296 1 0 0 1 0 1 240rgb x 304 304 g1 to g304 1 0 0 1 1 0 240rgb x 312 312 g1 to g312 1 0 0 1 1 1 240rgb x 320 320 g1 to g320 note: a fp (front porch) and bp (back porch) period will be inserted as blanking period (all gates output vgl level) before / after the driver scan through all of the scans free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 120 lcd driving waveform control (r02h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 0 0 0 0 0 0 0 gud 0 sinv fld 1 fld 0 0 0 b/c eor defaul t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 notes: 1. fld function is not available when the external display interface (i.e. rgb) is in use. 2. the 2-line interlaced display is functioned by fld=11. 3. on the 2 phase gate clock method, the gclk3b and gclk4b are used for the generation of vcom signal in the ltps panel. gud: this bit is for the gate scan direction. see the following table for the set up value. table 7.2.2 association and function chart for scanning fld, gud fld[1:0] gud scanning method and gate clock direction 0 forward scan direction: g1 ? g2 ? g3 ? ??. ? g320 ? g1 ? g2 ? ? forward gate clock direction: gspb/gclk2b ? gclk1b ? gclk2b ? gclk1 ??? (1 st frame), frame end (dummy 3 line over),. gspb/gclk2b ? gclk1b ? gclk2b ? ??. ? (2 nd frame) forward vcom clock direction: gclk4b ? gclk3b ? gclk4b ? gclk3b ..... (1 st frame), frame end (dummy 3 line over),. gspb/gclk3b ? gclk4b ? gclk3b ? ??...? (2 nd frame) 00 1 backward scan direction: g320 ? g319 ? g318 ? ??. ? g1 ? g320 ? g319 ? ? backward gate clock direction: gspb/ gclk1b ? gclk2b ? gclk1b ? ?.??......... (1 st frame), frame end (dummy 3 line over),. gspb/gclk1b ? gclk2b ? gclk1b ? ??? (2 nd frame) backward vcom clock direction: gspb/ gclk3b ? gclk4b ? gclk3b ? ?.???? (1 st frame), frame end (dummy 3 line over),. gspb/gclk4b ? gclk3b ? gclk4b ? ?...? (2 nd frame) 0 forward scan direction : g1 ? g2 ? g3 ? ??. ? g320 ? g1 ? g2 ? ? forward gate clock direction : gclk1b ? gclk2b ? gclk3b ? gclk4b ? gclk1b ? ? 01 1 backward scan direction : g320 ? g319 ? g318 ? ??. ? g1 ? g320 ? g319 ? ? backward gate clock direction : gclk4b ? gclk3b ? gclk2b ? gclk1b ? gclk4b ? ? 0 forward scan direction: g1 ? g2 ? g3 ? ??. ? g320 ? g1 ? g2 ? g3 ? ?? forward gate clock direction: lgspb/lgclk4b ? rgspb/rgclk4b ? lgclk1b ? rgclk1b ? lgclk2b ? rgclk2b ? ???. frame end (dummy 6 line over), lgspb/lgclk4b ? rgspb/rgclk4b ? lgclk1b ? ? 10 1 backward scan direction: g320 ? g319 ? g318 ? ??. ? g1 ? g320 ? g319 ? ?? backward gate clock direction: rgspb/rgclk1b ? lgspb/lgclk1b ? rgclk4b ? lgclk4b ? rgclk3b ? lgclk3b ? ???. frame end (dummy 6 line over), rgspb/rgclk1b ? lgspb/lgclk1b ? rgclk4b ? ?? 0 forward scan direction: g1 ? g3 ? g5 ? ??. ? g319 ? g2 ? g4 ? g6 ? ? g320 ? ? forward gate clock direction: lgspb/lgclk4b ? lgclk1b/rgclk1b ? lgclk2b/gclk2b ? lgclk3b/rgclk3b ? lgclk4b/rgclk4b ? ?. frame end (dummy 3 line over), rgspb/rgclk4b ? rgclk1b/lgclk1b ? rgclk2b/lgclk2b ? ? 11 1 backward scan direction: g320 ? g318 ? g316 ? ?. ? g2 ? g319 ? g317 ? ? g1 ? ? backward gate clock direction: rgspb/rgclk1b ? rgclk4b/lgclk4b ? rgclk3b/ lgclkb ? rgclk2b/lgclk2b ? rgclk1b/lgclk1b ? ?. frame end (dummy 3 line over), lgspb/lgclk1b ? lgclk4b/rgclk4b ? lgclk3b/rgclk3b ? ? free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 121 sinv: inverts the polarity of source output value when fld = 00 (2 phase gate drive method). table 7.2.3 sinv function description sinv function 0 source output data follows the polarity of gclk3b 1 source output data follows the polarity of gclk4b fld[1:0]: these bits are for the set up of the interlaced driver?s n raster-row. see the following table and figure for the set up value, field raster-row and scanning method. table 7.2.4 association chart for scanning fld and n raster-row fld [1:0] scanning method 00 1 field, 2 phase gate driving mode 01 1 field, 4 phase gate driving mode 10 2 field (normal mode), 4 phase gate driving mode 11 2 field (interlaced mode), 4 phase gate driving mode g1 g2 g3 .... g318 g319 g320 tft panel - when fld = 00, or 10 (normal scanning) g1 g3 g5 ..... g319 tft panel g2 g4 g6 ..... g320 tft panel 1 frame frame 1/2 frame 2/2 (b) when fld = 11 (2 field interlaced scanning) figure 7.2.1 interlaced scanning method b/c: when b/c = 0, a frame inversion waveform is generated and it alternates at every frame. when b/c = 1, n raster-row ac waveform is generated and alternates in each raster-row specified by bits eor in the lcd-driving-waveform control register (r02h). free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 122 eor: when the line inversion waveform is set (b/c = 1) and eor = 1, the odd/even frame-select signals is selected, and the n- raster-row reversed signals are being exclusive-or?ed (eor) for alternating drive. when the eor is used, the number of the lcd drive raster-row and the n raster-row alternates the lcd. b/c, eor inversion 0 0 frame inversion 0 1 setting prohibit 1 0 1-line inversion only 1 1 1-line inversion with frame inversion figure 7.2.2 frame / line inversion timing free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 123 entry mode (r03h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 tri dfm 0 bgr 0 0 0 0 0 0 0 0 am 0 i/d1 i/d0 defaul t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 tri: this bit is active on the 80-system of 8-bit bus interface and the data for 1-pixel is transported to the memory for 3 write cycles. this bit is on the 80-system of 16-bit interface and the data for 1-pixel is transported to the memory for 2 write cyc les. when the 80-system interface mode is not set in the 8-bit or16-bit mode, set tri bit to be ?0?. dfm: when 8-bit or 16-bit 80 interface mode and tri bit =1, dfm defines color depth for the ic. 16-bit (80-system), dfm = 0: 262k-color mode (16-bit, 2-bit data transfer to gram) 16-bit (80-system), dfm = 1: 262k-color mode (2-bit, 16-bit data transfer to gram) 8-bit (80-system), dfm = 0: 262k-color mode (3 times of 6-bit data transfer to gram) 8-bit (80-system), dfm = 1: 65k-color mode (5-bit, 6-bit, 5-bit data transfer to gram) bgr: after writing 18-bit data to gram, it is changed from into . db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 write data to gram *1 18 bits conversion of rgb to bgr (vice versa) gram figure 7.2.3 write data to gram via rgb swapping block this bit functions on the rgb swapping in the front of gram . it supports on the bgr format from cpu i/f and the bgr sub pixels of wrong manufacturing in making ltps panel. bgr bit cpu i/f data format panel sub pixel structure 0 bgr bgr 1 rgb bgr 1 bgr rgb 0 rgb rgb free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 124 am: set the automatic update method of the ac after the data is written to gram. when am = ?0?, the data is continuously written in horizontally. when am = ?1?, the data is continuously written vertically. when wi ndow addresses are specified, the gram in the window range can be written to according to the id[1:0] and am. i/d [1:0]: when id[1], id[0] = 1, the address counter (ac) is automatically increased by 1 after the data is written to the gram. when id[1], id[0] = 0, the ac is automatically decreased by 1 after the data is written to the gram. the increment/decrement setting of the address counter using id[1:0] is done independently for the horizontal address and vertical address. id[1:0] = ?00? h: decrement v: decrement id[1:0] = ?01? h: increment v: decrement id[1:0] = ?10? h: decrement v: increment id[1:0] = ?11? h: increment v: increment am=?0? horizontal update am=?1? vertical update note: when window addresses have been set, the gram can only be written within the window. when am or id is set, the start address should be written accordingly prior to memory write. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 125 oscillator control (r04h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 0 0 rad j5 rad j4 rad j3 rad j2 rad j1 rad j0 0 0 0 0 0 0 0 osc_ on defaul t 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 radj [5:0]: select the oscillation frequency of internal oscillator. radj[5:0] oscillation speed radj[5:0] oscillation speed 00_0000 setting disabled 10_0000 x0.873 00_0001 setting disabled 10_0001 x0.888 00_0010 setting disabled 10_0010 x0.901 00_0011 setting disabled 10_0011 x0.915 00_0100 setting disabled 10_0100 x0.934 00_0101 setting disabled 10_0101 x0.945 00_0110 setting disabled 10_0110 x0.962 00_0111 setting disabled 10_0111 x0.977 00_1000 setting disabled 10_1000 x1.0 default 00_1001 x0.64 10_1001 x1.02 00_1010 x0.646 10_1010 x1.04 00_1011 x0.654 10_1011 x1.06 00_1100 x0.663 10_1100 x1.08 00_1101 x0.670 10_1101 x1.10 00_1110 x0.678 10_1110 x1.12 00_1111 x0.685 10_1111 x1.14 01_0000 x0.699 11_0000 x1.18 01_0001 x0.705 11_0001 x1.2 01_0010 x0.714 11_0010 x1.23 01_0011 x0.722 11_0011 x1.25 01_0100 x0.734 11_0100 x1.29 01_0101 x0.743 11_0101 x1.32 01_0110 x0.753 11_0110 x1.35 01_0111 x0.761 11_0111 x1.38 01_1000 x0.776 11_1000 x1.43 01_1001 x0.784 11_1001 x1.46 01_1010 x0.797 11_1010 x1.50 01_1011 x0.807 11_1011 x1.54 01_1100 x0.822 11_1100 x1.59 01_1101 x0.832 11_1101 x1.63 01_1110 x0.844 11_1110 x1.68 01_1111 x0.855 11_1111 x1.73 note: setting example: if the default oscillation frequency is 1mhz and the register setting of radj [5:0] is 001100, internal osci llator oscillation frequency is 1mhz x 0.663 = 663khz. osc_on: the start oscillation instruction restarts the osci llator from the halt state in the stand-by mode. after this instruction, wait for at least 10 ms for the oscillation to stabilize before giving the next instruction. (see the stand-by mode section.) free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 126 display control 1 (r07h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 pt1 pt0 vle 2 vle 1 0 0 0 spt 0 gon cl rev 0 0 d1 d0 defaul t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pt1-0: normalize the source outputs when non-displayed area of the partial display is driven. source output on non- display area vcom output on non-display area cl pt1 * pt0 positive negative positive negative gate clock output for non- display area 0 0 0 vgs vgs vcoml vcoml 0 0 1 vgs gvdd vcoml vcomh 0 1 0 gvdd vgs vcoml vcomh 0 1 1 setting prohibit operating 1 0 0 avss avss vcoml vcoml 1 0 1 avss gvdd vcoml vcomh 1 1 0 gvdd avss vcoml vcomh 1 1 1 setting prohibit operating notes: when fld = ?00?, pt = ?00? is not available. and vcom output on the blanking area is always toggled. vle2?1 : when vle1 = 1, a vertical scroll is performed in the 1 st screen. when vle2 = 1, a vertical scroll is performed in the 2 nd screen. vertical scrolling on the two screens cannot be controlled at the same time. vle2 vle1 2 nd screen 1 st screen 0 0 fixed display fixed display 0 1 fixed display scroll 1 0 scroll fixed display 1 1 setting disabled setting disabled spt: when spt = 1, the 2-division lcd drive is performed. for details, see the screen-division driving function section. notes: this function is not available when the external display interface (i.e. rgb interface or vsync interface) is in use. gon: gate on/off control signal. all gate outputs are set to be gate off level when gon = 0. when gon = 1, gate driver is working: g1 to g320 output is either vgh or vglrout level. see the instruction set up flow for further description on the displ ay on/off flow. gon gate output 0 all gates off (all gates outputs are set to vgh) 1 gate on(vgh / vglrout) cl: cl = 1 selects 8-color display mode. for details, see the section on 8-color display mode. cl number of display colors 0 262,144 colors 1 8 colors free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 127 rev: when the rev = 1, all character and graphics display sections display with reversal. since the grayscale level can be reversed, display of the same data is enabled on normally white and normally black panels. display area rev gram data positive negative 0 6?b000000 : 6?b111111 v63 : v0 v0 : v63 1 6?b000000 : 6?b111111 v0 : v63 v63 : v0 d1?0: when d1 is 1, display is on. and, when d1 is 0, display is off. when display is off, the display data remains in the gram, and can be re-displayed instantly by setting ?d1 = 1?. when d1 is 0, the display is off with the entire source outputs set to t he vss level. because of this, the S6D1121 can control the charging current for the lcd with ac driving. control the display on/off wh ile control gon. for details, see the instruction set up flow. when d1?0 = 01, the internal display of the S6D1121 is performed although the display is off. when d1-0 = 00, the internal display operation halts and the display is off. d1 d0 gon source output gate output vcom output internal display operation 0 0 0 avss vgh avss halt 0 1 1 avss operate avss operate 1 0 1 blank display operate operate operate 1 1 1 normal display operate operate operate notes: 1. writing from mcu to gram is independent of d1?0. 2. in sleep and stand-by mode, d1?0 = 00. however, the register contents of d1?0 are not modified. 3. when source output is in the same phase with vcom, white screen is displayed at normally white lcd panel free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 128 display control 2 (r08h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 fmp 1 fmp 0 0 0 fp3 fp2 fp1 fp0 0 0 0 0 bp3 bp2 bp1 bp0 defaul t 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 the blanking period in the start and end of the display area c an be defined using this register. when n-raster-row is driving, a blank period is inserted after all screens are drawn. front and back porch can be adjusted using fp3-0 and bp3-0 bits (r08h). fmp1-0: set the output timing of frame cycle signal (frame maker). when fmp [1:0] = 2?b00, a high active pulse flm is output at the start of front porch period 1h period. make sure of 2?b00 fmp fp + bp. table 7.2.5 examples of using fmp function with fp and bp bits fmp1 fmp0 fp=1, bp=3 fp=2, bp=2 fp=3, bp=3 fp=1, bp=5 0 0 fp1 fp1 fp1 fp1 0 1 bp1 fp2 fp2 bp1 1 0 bp2 bp1 fp3 bp2 1 1 bp3 bp2 bp1 bp3 figure 7.2.4 flm signal generation timing notes: 1. in the case of starting point of first frame, the starting point of the fastest flm signal is bp1. the other frame is normal operation. 2. from figure 7.2.4, the case1 is fmp=2?b00, and the case2 is fmp=2?b11. 3. the first waveform of flm is always fixed on the bp1 period, and the other flm signal is followed the setting of fmp registe r value. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 129 fp3-0/bp3-0: set the periods of blanking (the front and back porch), which are placed at the beginning and end of the display. fp3-0 is for a front porch and bp3-0 is for a back porch. when front and back porches are set, the settings should meet the following conditions. 4 bp + fp 16 raster-rows 2 phase gate clock type: fp 1 raster-rows, bp 3 raster-rows 4 phase gate clock type: fp 2 raster-rows, bp 2 raster-rows when the external display interface is in use, the back porch (bp) will start on the falling edge of the vsync signal and the display operation will commence at the end of the back-porch period. the front porch (fp) will start when data for the number o f raster-rows specified by the nl bits has been displayed. during the period between the completion of the front-porch period and the next vsync signal, the display will remain blank. table 7.2.6 front / back porch fp3 bp3 fp2 bp2 fp1 bp1 fp0 bp0 # of raster periods in the front porch (2 phase gate clock) # of raster periods in the front porch (4 phase gate clock) # of raster periods in the back porch (4 phase gate clock) # of raster periods in the back porch (2 phase gate clock) 0 0 0 0 setting disabled setting disabled setting disabled setting disabled 0 0 0 1 1 setting disabled setting disabled setting disabled 0 0 1 0 2 2 2 setting disabled 0 0 1 1 3 3 3 3 0 1 0 0 4 4 4 4 . . . . . . . . . . . . . . . . . . . . . . . . 1 1 0 0 12 12 12 12 1 1 0 1 13 13 13 13 1 1 1 0 14 14 14 14 1 1 1 1 setting disabled setting disabled setting disabled setting disabled note: in the interlace drive mode, fp and bp setting is ignored: total sum of blanking period between 2 frames is automatically set to be 12 raster-rows. in the case of internal display mode, fp and bp settings are automatically set to be 8 raster-rows. in rgb and vsync mode, bp + fp value must be even. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 130 frame cycle control 1 (r0ah): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 0 0 0 0 ecs 3 ecs 2 ecs 1 ecs 0 0 0 0 rtn 4 rtn 3 rtn 2 rtn 1 rtn 0 defaul t 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 ecs: ecs period is sustained for the number of clock cycle which is set on ecs 3-0. ecs period rgb i/f operation (synchronized with dotclk) ecs3 ecs2 ecs1 ecs0 internal operation (synchronized with internal clock) 18-/16-bit 6-bit 0 0 0 0 0 0 0 0 0 0 1 1 clock cycle 4 clock cycle 12 clock cycle 0 0 1 0 2 clock cycle 8 clock cycle 24 clock cycle 0 0 1 1 3 clock cycle 12 clock cycle 36 clock cycle 0 1 0 0 4 clock cycle 16 clock cycle 32 clock cycle 0 1 0 1 5 clock cycle 20 clock cycle 60 clock cycle 0 1 1 0 6 clock cycle 24 clock cycle 72 clock cycle 0 1 1 1 7 clock cycle 28 clock cycle 84 clock cycle 1 0 0 0 8 clock cycle 32 clock cycle 96 clock cycle 1 0 0 1 9 clock cycle 36 clock cycle 108 clock cycle 1 0 1 0 10 clock cycle 40 clock cycle 120 clock cycle 1 0 1 1 11 clock cycle 44 clock cycle 132 clock cycle 1 1 0 0 12 clock cycle 48 clock cycle 144 clock cycle 1 1 0 1 13 clock cycle 52 clock cycle 156 clock cycle 1 1 1 0 14 clock cycle 56 clock cycle 168 clock cycle 1 1 1 1 15 clock cycle 60 clock cycle 180 clock cycle note : ecs period must be less than r_stp value. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 131 rtn4-0: set the 1h period (1 raster-row). rtn4 rtn3 rtn2 rtn1 rtn0 horizontal clock frequency (cl1) clock frequency for step-up circuits (dcclk) 0 0 0 0 0 32 clock cycle 0 0 0 0 1 33 clock cycle fosc / 16 0 0 0 1 0 34 clock cycle 0 0 0 1 1 35 clock cycle fosc / 17 0 0 1 0 0 36 clock cycle 0 0 1 0 1 37 clock cycle fosc / 18 0 0 1 1 0 38 clock cycle 0 0 1 1 1 39 clock cycle fosc / 19 0 1 0 0 0 40 clock cycle 0 1 0 0 1 41 clock cycle fosc / 20 0 1 0 1 0 42 clock cycle 0 1 0 1 1 43 clock cycle fosc / 21 0 1 1 0 0 44 clock cycle 0 1 1 0 1 45 clock cycle fosc / 22 0 1 1 1 0 46 clock cycle 0 1 1 1 1 47 clock cycle fosc / 23 1 0 0 0 0 48 clock cycle 1 0 0 0 1 49 clock cycle fosc / 24 1 0 0 1 0 50 clock cycle 1 0 0 1 1 51 clock cycle fosc / 25 1 0 1 0 0 52 clock cycle 1 0 1 0 1 53 clock cycle fosc / 26 1 0 1 1 0 54 clock cycle 1 0 1 1 1 55 clock cycle fosc / 27 1 1 0 0 0 56 clock cycle 1 1 0 0 1 57 clock cycle fosc / 28 1 1 0 1 0 58 clock cycle 1 1 0 1 1 59 clock cycle fosc / 29 1 1 1 0 0 60 clock cycle 1 1 1 0 1 61 clock cycle fosc / 30 1 1 1 1 0 62 clock cycle 1 1 1 1 1 63 clock cycle fosc / 31 free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 132 frame cycle control 2 (r0bh): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dcr 2 dcr 1 dcr 0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 dcr 2-0: set clock cycle for step-up circuit in external interface mode. please set dm bit to ?10? and dcr2-0 value when external interface is in use. in this case, dotclk must be input periodically and continuously. the external clock is the dcclk (clock cycle for step-up circui t) source, when external interface mode is in use (dm =?10?). clock cycle for step-up circuits (dcclk) in external interface mode dcr2 dcr1 dcr0 18-/16-bit 6-bit 0 0 0 dotclk/64 dotclk/192 0 0 1 dotclk/96 dotclk/288 0 1 0 dotclk/112 dotclk/336 0 1 1 dotclk/128 dotclk/384 1 0 0 dotclk/144 dotclk/432 1 0 1 dotclk/160 dotclk/480 1 1 0 dotclk/192 dotclk/576 1 1 1 dotclk/224 dotclk/672 note: if external input clock cycle is variable or discontinuous, clock cycle for step-up circuit must be generated internally (rm=0 ). free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 133 external interface control (r0ch): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 0 0 0 0 0 0 0 0 0 rm dm1 dm0 0 0 rim1 rim0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rm: specifies the interface for ram accesses. when the display data is written via the rgb interface, rm bit should be set (rm = 1). this bit and the dm bits can be set independently. the display data can be written via the system interface by clearing t his bit while the rgb interface is used. rm interface for ram access 0 system interface / vsync interface 1 rgb interface note: ?rm=0 & dm =01? is not supported. dm1-0: specify the display operation mode. the interface operatio n is based on the bits of dm1-0. this setting enables switchin g interface between internal operation and the external display interf ace. switching among two external display interfaces (rgb a nd vsync interface) should not be done. the external clock is the dcclk (clock cycle for step-up circuit) source, when external interface mode is in use (dm =?01?). dm1 dm0 display operation mode display operation mode in mddi 0 0 internal clock operation internal clock operation 0 1 rgb interface disable 1 0 vsync interface vsync interface 1 1 setting prohibit setting prohibit note: in case of ?rm=0 and dm =01?, must be write 1 frame image data to gram in 1 frame before. rim1-0: specify the rgb interface mode when the rgb interface is used. specifically, this setting specifies the mode when the bits of dm and rm are set to rgb interface. these bits should be set before display operation through the rgb interface and should not be set during operation. rim1 rim0 rgb interface mode 0 0 18-bit rgb interface (one transfer/pixel) 0 1 16-bit rgb interface (one transfer /pixel) 1 0 6-bit rgb interface (three transfers /pixel) 1 1 setting disable / prohibit depending on the external display interface setting, various interfaces can be specified to match the display state. while displaying motion picture on the rgb interface, the data for display can be written in high-speed write mode. this method can achieve both low power consumption and high-speed access. table 7.2.7 display state and interface display state operation mode ram access (rm) display operation mode (dm) still pictures or motion picture display internal clock system interface (rm=0) internal clock (dm=00) motion picture display rgb interface rgb interface (rm=1) rgb interface (dm=01) motion picture display vsync interface system interface (rm=0) vsync interface (dm1-0=10) notes: 1) the instruction register can only be set through the system interface. 2) rgb interface modes should not be set during operation. 3) for the transition flow for each operation mode, see the external display interface section. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 134 power control 1 (r10h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slp stb default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slp: when slp is high, the S6D1121 enters the sleep mode. the internal display operations are halted except for the r-c oscillator for reducing current consumption. only the following instructions except of some commands (*note) can be executed during the sleep mode. during the sleep mode, the other gram data do not updated. register set-up is maintained. note: some commands which are d1, d0, and gon stb: when stb is high, the S6D1121 enters the standby mode, where display operation completely stops. this mode can halt all the internal operations including the internal r-c oscillator. further, no external clock pulses are supplied. for details, see the standby mode section. level condition vcom avss ltps (gate clock / rgb multiplexer clock) vgh source avss free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 135 power control 2 (r11h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 0 0 vrh 5 vrh 4 vrh 3 vrh 2 vrh 1 vrh 0 0 0 vci1 _off 0 0 vc2 vc1 vc0 defaul t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 vrh5-0: set the amplified factor of the gvdd voltage (the voltage for the gamma voltage). it allows amplify from 3.0v to 5.0v vrh5 vrh4 vrh3 vrh2 vrh1 vrh0 gvdd vrh5 vrh4 vrh3 vrh2 vrh1 vrh0 gvdd 0 0 0 0 0 0 3.00v 1 0 0 0 0 0 4.01v 0 0 0 0 0 1 3.03v 1 0 0 0 0 1 4.05v 0 0 0 0 1 0 3.06v 1 0 0 0 1 0 4.08v 0 0 0 0 1 1 3.09v 1 0 0 0 1 1 4.11v 0 0 0 1 0 0 3.12v 1 0 0 1 0 0 4.14v 0 0 0 1 0 1 3.16v 1 0 0 1 0 1 4.17v 0 0 0 1 1 0 3.19v 1 0 0 1 1 0 4.21v 0 0 0 1 1 1 3.22v 1 0 0 1 1 1 4.24v 0 0 1 0 0 0 3.25v 1 0 1 0 0 0 4.27v 0 0 1 0 0 1 3.28v 1 0 1 0 0 1 4.30v 0 0 1 0 1 0 3.31v 1 0 1 0 1 0 4.33v 0 0 1 0 1 1 3.35v 1 0 1 0 1 1 4.36v 0 0 1 1 0 0 3.38v 1 0 1 1 0 0 4.40v 0 0 1 1 0 1 3.41v 1 0 1 1 0 1 4.43v 0 0 1 1 1 0 3.44v 1 0 1 1 1 0 4.46v 0 0 1 1 1 1 3.47v 1 0 1 1 1 1 4.49v 0 1 0 0 0 0 3.51v 1 1 0 0 0 0 4.52v 0 1 0 0 0 1 3.54v 1 1 0 0 0 1 4.56v 0 1 0 0 1 0 3.57v 1 1 0 0 1 0 4.59v 0 1 0 0 1 1 3.60v 1 1 0 0 1 1 4.62v 0 1 0 1 0 0 3.63v 1 1 0 1 0 0 4.65v 0 1 0 1 0 1 3.66v 1 1 0 1 0 1 4.68v 0 1 0 1 1 0 3.70v 1 1 0 1 1 0 4.71v 0 1 0 1 1 1 3.73v 1 1 0 1 1 1 4.75v 0 1 1 0 0 0 3.76v 1 1 1 0 0 0 4.78v 0 1 1 0 0 1 3.79v 1 1 1 0 0 1 4.81v 0 1 1 0 1 0 3.82v 1 1 1 0 1 0 4.84v 0 1 1 0 1 1 3.86v 1 1 1 0 1 1 4.87v 0 1 1 1 0 0 3.89v 1 1 1 1 0 0 4.91v 0 1 1 1 0 1 3.92v 1 1 1 1 0 1 4.94v 0 1 1 1 1 0 3.95v 1 1 1 1 1 0 4.97v 0 1 1 1 1 1 3.98v 1 1 1 1 1 1 5.00v vci1_off : vci1 amp off register. if vci1_off = h, vci1 pad and vci pad external short figure 7.2.5 the circuit for vci1_off funcion free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 136 vc2-0: set the vci1 voltage. these bits set the vci1 voltage from 0.68 to 1 times of the vci_ref voltage.vci1 is avdd reference voltage. vc2 vc1 vc0 vci1 0 0 0 0.68 x vci_ref 0 0 1 0.83 x vci_ref 0 1 0 0.92 x vci_ref 0 1 1 1.00 x vci_ref 1 0 0 0.575 x vci_ref note: don?t set any higher vci1 level than 3.0v free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 137 power control 3 (r12h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 0 0 0 0 0 0 0 0 0 sap 2 sap 1 sap 0 0 dc2 dc1 dc0 default 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 sap2-0: adjust the amount of fixed current from the fixed current s ource in the operational amplifier for the source driver. w hen the amount of fixed current is large, lcd driving ability and the display quality become high, but the current consumption is increased. adjust the fixed current considering the display quality and the current consumption. during non-display, when sap2- 0 = ?000?, the current consumption can be reduced by ending the operational amplifier and step-up circuit operation. sap2 sap1 sap0 amount of current in operational amplifier 0 0 0 source amp halt 0 0 1 low 0 1 0 medium low 0 1 1 medium 1 0 0 medium high 1 0 1 large 1 1 0 medium large 1 1 1 largest dc2-0: the operating frequency in the step-up circuit is selected. when the step-up operating frequency is high, the driving ability of the step-up circuit and the display quality become high, but the current consumption is increased. adjust the frequency considering the display quality and the current consumption. dc2 dc1 dc0 step-up cycle in step-up circuit 1,3 step-up cycle in step-up circuit 2 0 0 0 dcclk / 1 dcclk / 1 0 0 1 dcclk / 1 dcclk / 2 0 1 0 dcclk / 1 dcclk / 4 0 1 1 dcclk / 2 dcclk / 2 1 0 0 dcclk / 2 dcclk / 4 1 0 1 dcclk / 4 dcclk / 4 1 1 0 dcclk / 4 dcclk / 8 1 1 1 dcclk / 4 dcclk / 16 note: dcclk is clock frequency for step-up circuits free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 138 power control 4 (r13h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 vr2 c3 vr2 c2 vr2 c1 vr2 c0 vr1 c3 vr1 c2 vr1 c1 vr1 c0 vgl rc4 vgl rc3 vgl rc2 vgl rc1 vgl rc0 pon pon1 aon default 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 vr1c3-0: set the vr1 voltage. these bits set the vr1 voltage from 2.0 to 5.0. vr1 voltage is vgh, vgl reference voltage. vr2c3-0: set the vr2 voltage. these bits set the vr2 voltage from 2.0 to 5.0. vr2 voltage is vgh reference voltage. vr1c3 vr1c2 vr1c1 vr1c0 vr1 vr2c3 vr2c2 vr2c1 vr2c0 vr2 0 0 0 0 2.00 0 0 0 0 2.00 0 0 0 1 2.25 0 0 0 1 2.25 0 0 1 0 2.50 0 0 1 0 2.50 0 0 1 1 2.75 0 0 1 1 2.75 0 1 0 0 3.00 0 1 0 0 3.00 0 1 0 1 3.25 0 1 0 1 3.25 0 1 1 0 3.50 0 1 1 0 3.50 0 1 1 1 3.75 0 1 1 1 3.75 1 0 0 0 4.00 1 0 0 0 4.00 1 0 0 1 4.25 1 0 0 1 4.25 1 0 1 0 4.50 1 0 1 0 4.50 1 0 1 1 4.75 1 0 1 1 4.75 1 1 0 0 5.00 1 1 0 0 5.00 vgh: vgh voltage is gate positive voltage. vgh is generated by avdd + vr1 + vr2.vgh range is 7.5 ~ 16.0v vgl: vgl voltage is vglrout regulator power voltage. vgl is generated by ?(avdd + vr1). vgl range is ?11.0 ~ 5.5v vglrout: vglrout voltage is gate negative voltage. vglrout is generated by regulator amp. vglrc register is vglrout level control. vglrout range is ?10.5 ~ -5.0v vglrc4-0: set the vglrout voltage. these bits set the vglrout voltage from ?10.5 to -5.0. vglrout voltage is gate negative voltage. vglrc4 vglrc3 vglrc2 vglrc1 vglrc0 vglrout 0 0 0 0 0 -4.988 0 0 0 0 1 -5.250 0 0 0 1 0 -5.513 0 0 0 1 1 -5.775 0 0 1 0 0 -6.038 0 0 1 0 1 -6.300 0 0 1 1 0 -6.563 0 0 1 1 1 -6.825 0 1 0 0 0 -7.088 0 1 0 0 1 -7.350 0 1 0 1 0 -7.613 0 1 0 1 1 -7.875 0 1 1 0 0 -8.138 0 1 1 0 1 -8.400 0 1 1 1 0 -8.663 0 1 1 1 1 -8.925 1 0 0 0 0 -9.188 1 0 0 0 1 -9.450 1 0 0 1 0 -9.713 1 0 0 1 1 -9.975 1 0 1 0 0 -10.238 1 0 1 0 1 -10.500 free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 139 pon: this is an operation-starting bit for the booster circuit1. in case of pon = 0, the circuit is stopped and vice versa. for fur ther information about timing for adjusting to the pon = 1, please refer to the set up flow of power supply. pon1: this is an operation-starting bit for the booster circuit 2. in case of pon1 = 0, the circuit is stopped and vice versa. for further information about timing for adjusting to the pon1 = 1, please refer to the set up flow of power supply. aon: this is an operation-starting bit for the amplifier. in case of aon = 0, the circuit is stopped and vice versa. for further information about timing for adjusting to the aon= 1, please refer to the set up flow of power supply. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 140 power control 5 (r14h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 0 0 vcm 5 vcm 4 vcm 3 vcm 2 vcm 1 vcm 0 0 0 vml 5 vml 4 vml 3 vml 2 vml 1 vml 0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcm5-0: set the vcomdc voltage. voltage range is from 2.4 volt to 4.0 volt. using this command in case of coupling driving method. (vref = 2.0v) vcm 5 vcm 4 vcm 3 vcm 2 vcm 1 vcm 0 vcomdc voltage vcm 5 vcm 4 vcm 3 vcm 2 vcm 1 vcm 0 vcomdc voltage 0 0 0 0 0 0 2.40 v 1 0 0 0 0 0 3.21 v 0 0 0 0 0 1 2.43 v 1 0 0 0 0 1 3.24 v 0 0 0 0 1 0 2.45 v 1 0 0 0 1 0 3.26 v 0 0 0 0 1 1 2.48 v 1 0 0 0 1 1 3.29 v 0 0 0 1 0 0 2.50 v 1 0 0 1 0 0 3.31 v 0 0 0 1 0 1 2.53 v 1 0 0 1 0 1 3.34 v 0 0 0 1 1 0 2.55 v 1 0 0 1 1 0 3.37 v 0 0 0 1 1 1 2.58 v 1 0 0 1 1 1 3.39 v 0 0 1 0 0 0 2.60 v 1 0 1 0 0 0 3.42 v 0 0 1 0 0 1 2.63 v 1 0 1 0 0 1 3.44 v 0 0 1 0 1 0 2.65 v 1 0 1 0 1 0 3.47 v 0 0 1 0 1 1 2.68 v 1 0 1 0 1 1 3.49 v 0 0 1 1 0 0 2.70 v 1 0 1 1 0 0 3.52 v 0 0 1 1 0 1 2.73 v 1 0 1 1 0 1 3.54 v 0 0 1 1 1 0 2.76 v 1 0 1 1 1 0 3.57 v 0 0 1 1 1 1 2.78 v 1 0 1 1 1 1 3.59 v 0 1 0 0 0 0 2.81 v 1 1 0 0 0 0 3.62 v 0 1 0 0 0 1 2.83 v 1 1 0 0 0 1 3.64 v 0 1 0 0 1 0 2.86 v 1 1 0 0 1 0 3.67 v 0 1 0 0 1 1 2.88 v 1 1 0 0 1 1 3.70 v 0 1 0 1 0 0 2.91 v 1 1 0 1 0 0 3.72 v 0 1 0 1 0 1 2.93 v 1 1 0 1 0 1 3.75 v 0 1 0 1 1 0 2.96 v 1 1 0 1 1 0 3.77 v 0 1 0 1 1 1 2.98 v 1 1 0 1 1 1 3.80 v 0 1 1 0 0 0 3.01 v 1 1 1 0 0 0 3.82 v 0 1 1 0 0 1 3.03 v 1 1 1 0 0 1 3.85 v 0 1 1 0 1 0 3.06 v 1 1 1 0 1 0 3.87 v 0 1 1 0 1 1 3.09 v 1 1 1 0 1 1 3.90 v 0 1 1 1 0 0 3.11 v 1 1 1 1 0 0 3.92 v 0 1 1 1 0 1 3.14 v 1 1 1 1 0 1 3.95 v 0 1 1 1 1 0 3.16 v 1 1 1 1 1 0 3.97 v 0 1 1 1 1 1 3.19 v 1 1 1 1 1 1 4.00v note: set vcomdc range from 2.4v to 4.0v. (in the case of vref=2.0v) free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 141 vml5-0: set the vcoml voltage. voltage range is from 0 volt to 1.0 volt. (vref = 2.0v) vml 5 vml 4 vml 3 vml 2 vml 1 vml 0 amplitude of voltage vml 5 vml 4 vml 3 vml 2 vml 1 vml 0 amplitude of voltage 0 0 0 0 0 0 2.52 v 1 0 0 0 0 0 3.75 v 0 0 0 0 0 1 2.56 v 1 0 0 0 0 1 3.78 v 0 0 0 0 1 0 2.60 v 1 0 0 0 1 0 3.82 v 0 0 0 0 1 1 2.64 v 1 0 0 0 1 1 3.86 v 0 0 0 1 0 0 2.68 v 1 0 0 1 0 0 3.90 v 0 0 0 1 0 1 2.71 v 1 0 0 1 0 1 3.94 v 0 0 0 1 1 0 2.75 v 1 0 0 1 1 0 3.97 v 0 0 0 1 1 1 2.79 v 1 0 0 1 1 1 4.01 v 0 0 1 0 0 0 2.83 v 1 0 1 0 0 0 4.05 v 0 0 1 0 0 1 2.87 v 1 0 1 0 0 1 4.09 v 0 0 1 0 1 0 2.90 v 1 0 1 0 1 0 4.13 v 0 0 1 0 1 1 2.94 v 1 0 1 0 1 1 4.17 v 0 0 1 1 0 0 2.98 v 1 0 1 1 0 0 4.20 v 0 0 1 1 0 1 3.02 v 1 0 1 1 0 1 4.24 v 0 0 1 1 1 0 3.06 v 1 0 1 1 1 0 4.28 v 0 0 1 1 1 1 3.10 v 1 0 1 1 1 1 4.32 v 0 1 0 0 0 0 3.13 v 1 1 0 0 0 0 4.36 v 0 1 0 0 0 1 3.17 v 1 1 0 0 0 1 4.39 v 0 1 0 0 1 0 3.21 v 1 1 0 0 1 0 4.43 v 0 1 0 0 1 1 3.25 v 1 1 0 0 1 1 4.47 v 0 1 0 1 0 0 3.29 v 1 1 0 1 0 0 4.51 v 0 1 0 1 0 1 3.32 v 1 1 0 1 0 1 4.55 v 0 1 0 1 1 0 3.36 v 1 1 0 1 1 0 4.62 v 0 1 0 1 1 1 3.40 v 1 1 0 1 1 1 4.70 v 0 1 1 0 0 0 3.44 v 1 1 1 0 0 0 4.78 v 0 1 1 0 0 1 3.48 v 1 1 1 0 0 1 4.85 v 0 1 1 0 1 0 3.52 v 1 1 1 0 1 0 4.93 v 0 1 1 0 1 1 3.55 v 1 1 1 0 1 1 5.01 v 0 1 1 1 0 0 3.59 v 1 1 1 1 0 0 5.08 v 0 1 1 1 0 1 3.63 v 1 1 1 1 0 1 5.16 v 0 1 1 1 1 0 3.67 v 1 1 1 1 1 0 5.24 v 0 1 1 1 1 1 3.71 v 1 1 1 1 1 1 5.31 v note: set vcoml range from 0v to 1.0v. (in the case of vref=2.0v) free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 142 power control 6 (r15h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 vcm r 0 vma 5 vma 4 vma 3 vma 2 vma 1 vma 0 0 0 vmh 5 vmh 4 vmh 3 vmh 2 vmh 1 vmh 0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vcmr: if vcmr is low and direct driving method for vcom generation, vcomh is adjusted by vma5-0 register and vcomr pin is used to monitor the input voltage of the amp which outputs the vcomh voltage. and, if vcmr is low and coupling driving method for vcom generation, vcomh is adjusted by vma5-0 register and vcomr pin is used to monitor the input voltage of the amp which outputs the vcomh voltage. if vcmr is high and direct driving method for vcom generation, vma5-0 register is ignored and vcomh voltage is adjusted by external vcomr voltage. and, if vcmr is high and couplin g driving method for vcom generation, vma5-0 register is ignored and vcomh voltage is adjusted by external vcomr voltage. the relationship between vcomh and vcomr is given as vcomh=2.65 x vcomr. vcomr range is 1.328v ~ 2.0v vma5-0: set the vcomh voltage. voltage range is from 3.52 volt to 5.30 volt. (vref = 2.0v) vma 5 vma 4 vma 3 vma 2 vma 1 vma 0 vcomh voltage vma 5 vma 4 vma 3 vma 2 vma 1 vma 0 vcomh voltage 0 0 0 0 0 0 prohibit 1 0 0 0 0 0 4.26 v 0 0 0 0 0 1 prohibit 1 0 0 0 0 1 4.29 v 0 0 0 0 1 0 prohibit 1 0 0 0 1 0 4.32 v 0 0 0 0 1 1 prohibit 1 0 0 0 1 1 4.36 v 0 0 0 1 0 0 prohibit 1 0 0 1 0 0 4.39 v 0 0 0 1 0 1 prohibit 1 0 0 1 0 1 4.43 v 0 0 0 1 1 0 prohibit 1 0 0 1 1 0 4.46 v 0 0 0 1 1 1 prohibit 1 0 0 1 1 1 4.49 v 0 0 1 0 0 0 prohibit 1 0 1 0 0 0 4.53 v 0 0 1 0 0 1 prohibit 1 0 1 0 0 1 4.56 v 0 0 1 0 1 0 3.52 v 1 0 1 0 1 0 4.59 v 0 0 1 0 1 1 3.55 v 1 0 1 0 1 1 4.63 v 0 0 1 1 0 0 3.58 v 1 0 1 1 0 0 4.66 v 0 0 1 1 0 1 3.62 v 1 0 1 1 0 1 4.69 v 0 0 1 1 1 0 3.65 v 1 0 1 1 1 0 4.73 v 0 0 1 1 1 1 3.68 v 1 0 1 1 1 1 4.76 v 0 1 0 0 0 0 3.72 v 1 1 0 0 0 0 4.80 v 0 1 0 0 0 1 3.75 v 1 1 0 0 0 1 4.83 v 0 1 0 0 1 0 3.79 v 1 1 0 0 1 0 4.86 v 0 1 0 0 1 1 3.82 v 1 1 0 0 1 1 4.90 v 0 1 0 1 0 0 3.85 v 1 1 0 1 0 0 4.93 v 0 1 0 1 0 1 3.89 v 1 1 0 1 0 1 4.96 v 0 1 0 1 1 0 3.92 v 1 1 0 1 1 0 5.00 v 0 1 0 1 1 1 3.95 v 1 1 0 1 1 1 5.03 v 0 1 1 0 0 0 3.99 v 1 1 1 0 0 0 5.06 v 0 1 1 0 0 1 4.02 v 1 1 1 0 0 1 5.10 v 0 1 1 0 1 0 4.05 v 1 1 1 0 1 0 5.13 v 0 1 1 0 1 1 4.09 v 1 1 1 0 1 1 5.17 v 0 1 1 1 0 0 4.12 v 1 1 1 1 0 0 5.20 v 0 1 1 1 0 1 4.16 v 1 1 1 1 0 1 5.23 v 0 1 1 1 1 0 4.19 v 1 1 1 1 1 0 5.27 v 0 1 1 1 1 1 4.22 v 1 1 1 1 1 1 5.30 v note: set vcomh range from 3.52v to 5.3v. (in the case of vref=2.0v) vmh5-0: set the vcomprec voltage. voltage range is from 3.60 volt to 6.00 volt. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 143 (vref = 2.0v) vmh 5 vmh 4 vmh 3 vmh 2 vmh 1 vmh 0 vcomprec voltage vmh 5 vmh 4 vmh 3 vmh 2 vmh 1 vmh 0 vcomprec voltage 0 0 0 0 0 0 3.60 v 1 0 0 0 0 0 4.82 v 0 0 0 0 0 1 3.64 v 1 0 0 0 0 1 4.86 v 0 0 0 0 1 0 3.68 v 1 0 0 0 1 0 4.90 v 0 0 0 0 1 1 3.71 v 1 0 0 0 1 1 4.93 v 0 0 0 1 0 0 3.75 v 1 0 0 1 0 0 4.97 v 0 0 0 1 0 1 3.79 v 1 0 0 1 0 1 5.01 v 0 0 0 1 1 0 3.83 v 1 0 0 1 1 0 5.05 v 0 0 0 1 1 1 3.87 v 1 0 0 1 1 1 5.09 v 0 0 1 0 0 0 3.90 v 1 0 1 0 0 0 5.12 v 0 0 1 0 0 1 3.94 v 1 0 1 0 0 1 5.16 v 0 0 1 0 1 0 3.98 v 1 0 1 0 1 0 5.20 v 0 0 1 0 1 1 4.02 v 1 0 1 0 1 1 5.24 v 0 0 1 1 0 0 4.06 v 1 0 1 1 0 0 5.28 v 0 0 1 1 0 1 4.10 v 1 0 1 1 0 1 5.31 v 0 0 1 1 1 0 4.13 v 1 0 1 1 1 0 5.35 v 0 0 1 1 1 1 4.17 v 1 0 1 1 1 1 5.39 v 0 1 0 0 0 0 4.21 v 1 1 0 0 0 0 5.43 v 0 1 0 0 0 1 4.25 v 1 1 0 0 0 1 5.47 v 0 1 0 0 1 0 4.29 v 1 1 0 0 1 0 5.50 v 0 1 0 0 1 1 4.32 v 1 1 0 0 1 1 5.54 v 0 1 0 1 0 0 4.36 v 1 1 0 1 0 0 5.58 v 0 1 0 1 0 1 4.40 v 1 1 0 1 0 1 5.62 v 0 1 0 1 1 0 4.44 v 1 1 0 1 1 0 5.66 v 0 1 0 1 1 1 4.48 v 1 1 0 1 1 1 5.70 v 0 1 1 0 0 0 4.51 v 1 1 1 0 0 0 5.73 v 0 1 1 0 0 1 4.55 v 1 1 1 0 0 1 5.77 v 0 1 1 0 1 0 4.59 v 1 1 1 0 1 0 5.81 v 0 1 1 0 1 1 4.63 v 1 1 1 0 1 1 5.85 v 0 1 1 1 0 0 4.67 v 1 1 1 1 0 0 5.89 v 0 1 1 1 0 1 4.70 v 1 1 1 1 0 1 5.92 v 0 1 1 1 1 0 4.74 v 1 1 1 1 1 0 5.96 v 0 1 1 1 1 1 4.78 v 1 1 1 1 1 1 6.00 v note: set vcomprec range from 3.6v to 6.0v. (in the case of vref=2.0v) free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 144 power control 7 (r16h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 0 0 0 0 0 0 0 0 vcom _off 0 0 0 0 pre c com s com a default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 vcom_off: control on / off of the vcom, vcomprec and vcomdc in the 2 phase gate clock mode. prec: control the pre-charge signal for vcom. coms: selection signal for vcom driving method (direct or coupling). 1: direct vcom driving method 0: coupling vcom driving method coma: setup vcoml voltage. 1: vcoml = 0v ~1v(control vml[5:0]) 0: vcoml = avss table 7.2.8 functional table of direct vcom driving and coupling vcom driving method coms coma functions 1 using direct vcom driving type, vcoml level is an output of op amplifier. 1 0 using direct vcom driving type and vcoml level is avss. 1 using coupling vcom driving type, vcoml level is an output of op amplifier. 0 0 using coupling vcom driving type and vcoml level is avss. notes: when the setting value of fld = 00 (2 phase gate clock driving mode) is ?0?, the output signals relating vcom are useless. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 145 table 7.2.9 function configuration ta ble of direct vcom driving and coupling vcom driving method coms coma fld[1:0] vcom vcomprec vcomdc 00 avss avss avss 1 01,10,11 vcomh to vcoml avss avss 00 avss avss avss 1 0 01,10,11 vcomh to avss avss avss 00 avss avss avss 1 01,10,11 vcomh to vcoml after vmh setting value during prec period, this value is floating. vcm setting value 00 avss avss avss 0 0 01,10,11 vcomh to avss after vmh setting value during prec period, this value is floating. vcm setting value notes: when the setting value of fld = 00 (2 phase gate clock driving mode), panel is not use the vcom, vcomprec, and vcomdc. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 146 ram address set (r20h / r21h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 0 0 0 0 0 0 0 0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 defaul t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w 0 0 0 0 0 0 0 0 ad 16 ad 15 ad 14 ad 13 ad 12 ad 11 ad 10 ad9 ad8 defaul t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ad16?0: initially set gram addresses to the address counter (ac). once the gram data is written, the ac is automatically updated according to i/d bit settings. this allows consecutive accesses without resetting address. once the gram data is r ead, the ac is not automatically updated. gram address setting is not allowed in the standby mode. ensure that the address is set within the specified window address. when rgb interface is in use (rm1-0=10), ad16-0 will be set at the falling edge of the vsync signal. when the internal clock operation and vsync interface (rm=0x) are in use, ad16-0 will be set upon execution of an instruction. ad16 to ad0 gram setting ?00000?h to ?000ef?h bitmap data for g1 ?00100?h to ?001ef?h bitmap data for g2 ?00200?h to ?002ef?h bitmap data for g3 ?00300?h to ?003ef?h bitmap data for g4 : : : : : : ?13c00?h to ?13cef?h bitmap data for g317 ?13d00?h to ?13def?h bitmap data for g318 ?13e00?h to ?13eef?h bitmap data for g319 ?13f00?h to ?13fef?h bitmap data for g320 free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 147 read / write data to gram (r22h): gram write data: r/w rs ib17 ib16 ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 wdr [17:0] ( bit assignment from db or pd to wd varies with interface mode. ) wdr [17:0]: input data for gram can be expanded to 18 bits. the expansion format varies according to the interface method. the input data selects the grayscale level. after a write, the address is automatically updated according to am and i/d bit set tings. the gram cannot be accessed in standby mode. when 16- or 8-bit interface is in use, the write data is expanded to 18 bits by writing the msb of the data to its lsb. when written data to gram is used by rgb interface via the system interface, please make sure that writing data do not cause conflicts. when the 18-bit rgb interface is in use, 18-bit data is written to ram via pd17-0. this interface is available on the 262,144- colors. when the 16-bit rgb interface is in use, the msb is wri tten to its lsb. this interface is available on the 65,536-color s. gram read data: r/w rs ib17 ib16 ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 r 1 rdr [17:0] ( bit assignment from rd to db varies with interface mode. ) rdr [17:0]: read 18-bit data from the gram. when the data is read to the mcu, the first-word read immediately after the gram address setting is latched from the gram to the internal read -data latch. the data on the data bus (db15?0) becomes invalid and the second-word read is normal. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 148 gamma control 1 ~12 (r30h ~ r3bh): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 r/w 1 0 0 pkp1 [5:0] 0 0 pkp0 [5:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 1 0 0 pkp3 [5:0] 0 0 pkp2 [5:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 1 0 0 pkp5 [5:0] 0 0 pkp4 [5:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 1 0 0 pkp7 [5:0] 0 0 pkp6 [5:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 1 0 0 pkp9 [5:0] 0 0 pkp8 [5:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 1 0 0 pkp11 [5:0] 0 0 pkp10 [5:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 1 0 0 pkn1 [5:0] 0 0 pkn0 [5:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 1 0 0 pkn3 [5:0] 0 0 pkn2 [5:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 1 0 0 pkn5 [5:0] 0 0 pkn4 [5:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 1 0 0 pkn7 [5:0] 0 0 pkn6 [5:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 1 0 0 pkn9 [5:0] 0 0 pkn8 [5:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 1 0 0 pkn11 [5:0] 0 0 pkn10 [5:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 1 0 0 0 vrp1 [4:0] 0 0 0 vrp0 [4:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w 1 0 0 0 vrn1 [4:0] 0 0 0 vrn0 [4:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pkp11 ~ 0 [5:0]: the gamma fine adjustment register for the positive polarity output pkn11 ~ 0 [5:0]: the gamma fine adjustment register for the negative polarity output vrp1 [4:0]: the amplitude adjustment register for the positive polarity output vrn1 [4:0]: the amplitude adjustment register for the negative polarity output vrp0 [4:0]: the reference adjustment register for the positive polarity output vrn0 [4:0]: the reference adjustment register for the negative polarity output for details, see the gamma adjustment function. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 149 vertical scroll control (r41h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 vl8 vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vl8-0: specify scroll length at the scroll display for vertical smooth scrolling. any raster-row from the 1 st to 320 th can be scrolled according to the value of vl8-0. after 320 th raster-row is displayed, the display restarts from the first raster-row. the scroll length (vl8-0) is valid when vle1 = 1 or vle2 = 1. the raster-row display is fixed when vle2-1 = 00. vl8 vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 scroll length 0 0 0 0 0 0 0 0 0 0 raster-row 0 0 0 0 0 0 0 0 1 1 raster-row 0 0 0 0 0 0 0 1 0 2 raster-row . . . . . . 1 0 0 1 1 1 1 1 0 318 raster-row 1 0 0 1 1 1 1 1 1 319 raster-row notes: 1. don?t set any higher raster-row than 319 (?13f?h). 2. also, make sure that the condition of below table (table 7.2.9) table 7.2.10 vl setting value on the vertical scroll operation spt vle[1:0] vl setting value 0 x se1 ? ss1 vl (operation of scroll area 1 field) ?01? se1 ? ss1 vl (operation of scroll area 1 field) 1 ?10? se2 ? ss2 vl (operation of scroll area 2 field) figure 7.2.6 scroll function (ss1 = 0, se1 = 319, vl = 1, spt = 0) free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 150 1 st screen driving position (r42h / r43h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 se18 se17 se16 se15 se14 se13 se12 se11 se10 default 1 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 w 1 0 0 0 0 0 0 0 ss18 ss17 ss16 ss15 ss14 ss13 ss12 ss11 ss10 default 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 nd screen driving position (r44h / r45h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 se28 se27 se26 se25 se24 se23 se22 se21 se20 default 1 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 w 1 0 0 0 0 0 0 0 ss28 ss27 ss26 ss25 ss24 ss23 ss22 ss21 ss20 default 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ss18?10: specify the driving starting position for the first screen in a line unit. the lcd driving starts from the ?set value +1? gate driver. se18?10: specify the driving end position for the first screen in a line unit. the lcd driving is performed to the ?set value + 1? gate driver. for instance, when ss18?10 = 07h and se18?10 = 10h are set, the lcd driving is performed from g8 to g17, and non-display driving is performed for g1 to g7, g18, and others. ensure that ss18 to 10 se18 to 10 13fh. for details, see the screen-division driving function section. ss28?20: specify the driving start position for the second screen in a line unit. the lcd driving starts from the ?set value + 1? of the gate driver. the second screen is driven when spt = 1. se28?20: specify the driving end position for the second screen in a line unit. the lcd driving is performed to the ?set value + 1? of the gate driver. for instance, when spt = 1, ss28?20 = 20h, a nd se28?20 = 13fh are set, the lcd driving is performed from g33 to g320. ensure that ss18 to 10 se18 to 10 < ss28 to 20 se28 to 20 13fh. for details, see the screen-division driving function section. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 151 horizontal window address position (r46h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 hea 7 hea 6 hea 5 hea 4 hea 3 hea 2 hea 1 hea 0 hsa 7 hsa 6 hsa 5 hsa 4 hsa 3 hsa 2 hsa 1 hsa 0 default 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 vertical window address position (r47h / r48h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 vea 8 vea 7 vea 6 vea 5 vea 4 vea 3 vea 2 vea 1 vea 0 default 1 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 w 1 0 0 0 0 0 0 0 vsa 8 vsa 7 vsa 6 vsa 5 vsa 4 vsa 3 vsa 2 vsa 1 vsa 0 default 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 hsa7-0/hea7-0: specify the horizontal start/end positions of a window for access in memory. data can be written to the gram. the written data is from the address specified by hsa7-0 to the address specified by hea 7-0. note that an address must be set before ram data are written. ensure 00h hsa7-0 hea7-0 ? efh. vsa8-0/vea8-0: specify the vertical start/end positions of a window for access in memory. data can be written to the gram. the written data is from the address specified by vsa8-0 to the address specified by vea8-0. note that an address must be set before ram data are written. ensure 000h ? vsa8-0 ? vea8-0 ? 13fh. window address 0000 h 13fefh hsa hea vsa vea gram address s p ace window address settin g ran g e ? 00 ? h hea8-0 ? ef ? h ? 00 ? h vea8-0 ? 13f ? h note: 1. ensure that the window address area is within the gram address s p ace figure 7.2.7 window address setting range free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 152 mddi wake up control (r50h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wake _en default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wake_en: when wake_en is 1, client initiated wake-up is enabled. but parameter data ib[15:1] must be ?0000h?, otherwise, client initiated wake-up is disabled. mddi wake start position (r51h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 wkl 7 wkl 6 wkl 5 wkl 4 wkl 3 wkl 2 wkl 1 wkl 0 0 0 0 0 wkf 3 wkf 2 wkf 1 wkf 0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wkf3-0: when client initiated wake-up is used at mddi, the frame positi on that data is updated is set by the value of wkf 3-0. the range of wkf is from ?0000? to ?1111?. if wkf is ?0000?, data is updated at the first frame, and if ?1111? data update star ts after 16 th frame. wkl7-0: when client initiated wakeup is used at mddi, data is updated at the line the value of wkl7-0 in the frame that is set by wkl7-0. the wkl supports from ?00h? to ?ffh?. if wkl is ?00h?, data is updated at the first line, and if wkl is ?ffh?, data upd ate starts at the 256 th line. setting of wfk and wkl is needed for client-initiated link wake-up. for example, wkf is ?0010? and wkl is ?0001?, data is updated at second line of third frame. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 153 sub panel control 1 (r52h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 0 0 0 0 0 mode_sel [1:0] sub_im[1:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 mode_sel1-0 : set the stn and mpu interfaces mode_sel1 mode_sel0 interface 0 0 stn mode 0 1 setting prohibit 1 0 tft 80 mode 1 1 tft 68 mode sub_im1-0: set the bus width of sub-panel interface. sub_im1 sub_im0 interface 0 0 18bit 0 1 9bit 1 0 16bit 1 1 8bit free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 154 sub panel control 2 / 3 (r53h / r54h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 0 sub_sel[7:0] default 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 w 1 0 0 0 0 0 0 0 0 sub_wr[7:0] default 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 sub_sel: sub_sel is the index of main/sub panel selection. initial value of sub_sel is ?7ah?. in mddi mode, if written register address is ?7ah? (initial state: sub_sel is ?7ah?) and register data is ?0001h?, then main panel is selected, and if that is ?0 000h?, then sub panel is selected. using sub_sel register, main / sub panel selection index change is possible. sub_wr : sub_wr is the index of sub panel data write. initial value of sub_wr is ?22h?. when mddi host transfer gram data to sub panel driver ic via video stream packet, sub_wr (initially 22h), index for gram access is automatically transferred befo re gram data transfer. when sub panel driver ic uses other address, 22h address have to be changed. then user can change sub_wr value from 22h to other value free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 155 gpio control (r55h / r56h / r57h / r58h / r59h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 gpio_data[9:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w 1 0 0 0 0 0 0 gpio_con[9:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w 1 0 0 0 0 0 0 gpio_clr[9:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w 1 0 0 0 0 0 0 gpio_en[9:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w 1 0 0 0 0 0 0 gpio_pol[9:0] default 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 gpio_data: gpio input data value. when gpio is input mode, gpio value is set to the register. gpio_con: control of gpio pad direction, when gpio_con is ?0?, then gpio is input mode, and when gpio_con is ?1?, then gpio is output mode. gpio_clr : after gpio has an interrupt, gpio_clr clears specified gpio interrupt. gpio_en : enable specified gpio interrupt. when gpio is set input, if gpio_en is ?1?, it acts as enable internal interrupt. gpio_pol: control polarity setting of gpio interrupt. if the bit is set to ?1?, gpio interrupt happens at rising edge of gpin, if set to ?0?, it happens at falling edge. for more information about these registers, refer to gpio control section free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 156 mtp control (r60h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 0 0 0 0 0 0 0 0 0 0 0 0 mtp_ load mtp_ wrb mtp_ sel mtp_ erb default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 mtp_load : if mtp_load is set high (more 80ns), then mtp data latch from mtp cells to mtp port. default is low. mtp_wrb: mtp program enable signal, low active, it is only usable in stb or slp mode. default is high. r62h (test key command) should be set ?8c?h before this command. mtp_sel: mtp value (mtp vcomh) or instruction value (r15h vcomh) selection, if mtp_sel = 1, vcomh of mtp data is selected, else mtp_sel = 0, the value of instruction register vcomh (r15h) is selected. mtp_erb : mtp initial (erase) mode set. if mtp_erb = 0, mtp data are initialized to all zero. r62h (test key command) should be set ?8c?h before this command. figure 7.2.8 relation between r15h and mtp notes: in mddi mode, it doesn?t work at stb mode. so, it is only active at slp mode in mddi free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 157 mtp vcomh read (r61h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib1 w 0 0 0 0 0 0 0 0 0 0 mtp _d6 mtp_ d5 mtp_ d4 mtp_ d3 mtp_ d2 mtp _d1 mtp_ d1 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this command reads the vcom mtp read bits. read 7bit data from mtp cells. d6 is protection bit which should be high, when mtp is programming. if msb set to high, it canno t be write-protective. if you want to re-write, first initialize mtp, then mtp d6 set to low. mtp bit descriptions mtp_d6 protection mtp_d5 vma[5] mtp_d4 vma[4] mtp_d3 vma[3] mtp_d2 vma[2] mtp_d1 vma[1] mtp_d0 vma[0] mtp test key command (r62h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 this command is a key of some operations (ex. mtp_erb, mtp_wrb). if it is not matched with ?8c?, then some mtp command doesn?t operate. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 158 goe start / end timing control (r70h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 0 0 0 0 0 0 gost[1:0] 0 0 0 goed[4:0] default 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 gost: control of register bits for gate enable start timing. set up in the range 01h gost [1:0] 03h gost [1:0] osc clock (1 mhz) dotclk (18/16-bit, 5mhz) 0 0 0 clock cycle 0 clock cycle 0 1 1 clock cycle 1 clock cycle x 4 1 0 2 clock cycle 2 clock cycle x 4 1 1 3 clock cycle 3 clock cycle x 4 goed: control of register bits for gate enable end timing. set up in the range gost< goed rtn goed [4:0] osc clock (1 mhz) dotclk (18/16-bit, 5mhz) 0 0 0 0 0 32 clock cycle 32 clock cycle x 4 0 0 0 0 1 33 clock cycle 33 clock cycle x 4 0 0 0 1 0 34 clock cycle 34 clock cycle x 4 0 0 0 1 1 35 clock cycle 35 clock cycle x 4 0 0 1 0 0 36 clock cycle 36 clock cycle x 4 0 0 1 0 1 37 clock cycle 37 clock cycle x 4 0 0 1 1 0 38 clock cycle 38 clock cycle x 4 0 0 1 1 1 39 clock cycle 39 clock cycle x 4 0 1 0 0 0 40 clock cycle 40 clock cycle x 4 0 1 0 0 1 41 clock cycle 41 clock cycle x 4 0 1 0 1 0 42 clock cycle 42 clock cycle x 4 0 1 0 1 1 43 clock cycle 43 clock cycle x 4 0 1 1 0 0 44 clock cycle 44 clock cycle x 4 0 1 1 0 1 45 clock cycle 45 clock cycle x 4 0 1 1 1 0 46 clock cycle 46 clock cycle x 4 0 1 1 1 1 47 clock cycle 47 clock cycle x 4 1 0 0 0 0 48 clock cycle 48 clock cycle x 4 1 0 0 0 1 49 clock cycle 49 clock cycle x 4 1 0 0 1 0 50 clock cycle 50 clock cycle x 4 1 0 0 1 1 51 clock cycle 51 clock cycle x 4 1 0 1 0 0 52 clock cycle 52 clock cycle x 4 1 0 1 0 1 53 clock cycle 53 clock cycle x 4 1 0 1 1 0 54 clock cycle 54 clock cycle x 4 1 0 1 1 1 55 clock cycle 55 clock cycle x 4 1 1 0 0 0 56 clock cycle 56 clock cycle x 4 1 1 0 0 1 57 clock cycle 57 clock cycle x 4 1 1 0 1 0 58 clock cycle 58 clock cycle x 4 1 1 0 1 1 59 clock cycle 59 clock cycle x 4 1 1 1 0 0 60 clock cycle 60 clock cycle x 4 1 1 1 0 1 61 clock cycle 61 clock cycle x 4 1 1 1 1 0 62 clock cycle 62 clock cycle x 4 1 1 1 1 1 63 clock cycle 63 clock cycle x 4 note: don?t set over the range of setting rtn. also, make sure that gost + goed < 64 clocks. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 159 gsp clock delay control (r71h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 0 0 0 0 0 gsp_dly[3:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gsp_dly: control the starting of gate start pulse. gsp_dly[3:0] osc clock (1 mhz) dotclk (18/16-bit, 5mhz) 0 0 0 0 0 clock cycle 0 clock cycle 0 0 0 1 1 clock cycle 1 clock cycle x 4 0 0 1 0 2 clock cycle 2 clock cycle x 4 0 0 1 1 3 clock cycle 3 clock cycle x 4 0 1 0 0 4 clock cycle 4 clock cycle x 4 0 1 0 1 5 clock cycle 5 clock cycle x 4 0 1 1 0 6 clock cycle 6 clock cycle x 4 0 1 1 1 7 clock cycle 7 clock cycle x 4 1 0 0 0 8 clock cycle 8 clock cycle x 4 1 0 0 1 9 clock cycle 9 clock cycle x 4 1 0 1 0 10 clock cycle 10 clock cycle x 4 1 0 1 1 11 clock cycle 11 clock cycle x 4 1 1 0 0 12 clock cycle 12 clock cycle x 4 1 1 0 1 13 clock cycle 13 clock cycle x 4 1 1 1 0 14 clock cycle 14 clock cycle x 4 1 1 1 1 15 clock cycle 15 clock cycle x 4 free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 160 r source output start point (r72h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 0 0 0 0 0 0 r_stp[2:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 r_stp: the start timing of the red signal output from source in setup. r_stp[2:0] osc clock (1 mhz) dotclk (18/16-bit, 5mhz) 0 0 0 1 clock cycle 1 clock cycle x 4 0 0 1 5 clock cycle 5 clock cycle x 4 0 1 0 6 clock cycle 6 clock cycle x 4 0 1 1 7 clock cycle 7 clock cycle x 4 1 0 0 8 clock cycle 8 clock cycle x 4 1 0 1 9 clock cycle 9 clock cycle x 4 1 1 0 10 clock cycle 10 clock cycle x 4 1 1 1 11 clock cycle 11 clock cycle x 4 g source output start point (r73h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 0 0 0 0 0 0 g_stp[2:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 g_stp: the start timing of the green signal output from source in setup. set up in the range r_stp < g_stp r_stp + 15 clock cycle g_stp[2:0] osc clock (1 mhz) dotclk (18/16-bit, 5mhz) 0 0 0 8 clock cycle 8 clock cycle x 4 0 0 1 9 clock cycle 9 clock cycle x 4 0 1 0 10 clock cycle 10 clock cycle x 4 0 1 1 11 clock cycle 11 clock cycle x 4 1 0 0 12 clock cycle 12 clock cycle x 4 1 0 1 13 clock cycle 13 clock cycle x 4 1 1 0 14 clock cycle 14 clock cycle x 4 1 1 1 15 clock cycle 15 clock cycle x 4 free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 161 b source output start point (r74h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 0 0 0 0 0 0 b_stp[2:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 b_stp: control the start timing of the green signal output from source in setup. set up in the range g_stp (r_stp + g_stp) < b_stp 15 + g_stp (r_stp + b_stp). b_stp[2:0] osc clock (1 mhz) dotclk (18/16-bit, 5mhz) 0 0 0 8 clock cycle 8 clock cycle x 4 0 0 1 9 clock cycle 9 clock cycle x 4 0 1 0 10 clock cycle 10 clock cycle x 4 0 1 1 11 clock cycle 11 clock cycle x 4 1 0 0 12 clock cycle 12 clock cycle x 4 1 0 1 13 clock cycle 13 clock cycle x 4 1 1 0 14 clock cycle 14 clock cycle x 4 1 1 1 15 clock cycle 15 clock cycle x 4 r mux start pulse and width timing control (r75h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 m_rstp[1:0] 0 0 0 0 0 m_rpw[2:0] default 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 m_rstp: control the start timing of the catching the red signal output. set up in the range r_stp < m_rstp 3 + r_stp. m_rstp[1:0] osc clock (1 mhz) dotclk (18/16-bit, 5mhz) 0 0 disable disable 0 1 1 clock cycle 1 clock cycle x 4 1 0 2 clock cycle 2 clock cycle x 4 1 1 3 clock cycle 3 clock cycle x 4 m_rpw: control the pulse width timing of caching the red signal output. m_rpw[2:0] osc clock (1 mhz) dotclk (18/16-bit, 5mhz) 0 0 0 8 clock cycle 8 clock cycle x 4 0 0 1 9 clock cycle 9 clock cycle x 4 0 1 0 10 clock cycle 10 clock cycle x 4 0 1 1 11 clock cycle 11 clock cycle x 4 1 0 0 12 clock cycle 12 clock cycle x 4 1 0 1 13 clock cycle 13 clock cycle x 4 1 1 0 14 clock cycle 14 clock cycle x 4 1 1 1 disable disable free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 162 g mux start pulse and width timing control (r76h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 m_gstp[1:0] 0 0 0 0 0 m_gpw[2:0] default 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 m_gstp: control the start timing of catching the green signal output. set up in the range g_stp m_gstp 3 + g_stp. m_gstp[1:0] osc clock (1 mhz) dotclk (18/16-bit, 5mhz) 0 0 disable disable 0 1 1 clock cycle 1 clock cycle x 4 1 0 2 clock cycle 2 clock cycle x 4 1 1 3 clock cycle 3 clock cycle x 4 m_gpw: control the pulse width of catching the green signal output. m_gpw[2:0] osc clock (1 mhz) dotclk (18/16-bit, 5mhz) 0 0 0 8 clock cycle 8 clock cycle x 4 0 0 1 9 clock cycle 9 clock cycle x 4 0 1 0 10 clock cycle 10 clock cycle x 4 0 1 1 11 clock cycle 11 clock cycle x 4 1 0 0 12 clock cycle 12 clock cycle x 4 1 0 1 13 clock cycle 13 clock cycle x 4 1 1 0 14 clock cycle 14 clock cycle x 4 1 1 1 disable disable free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 163 b mux start pulse and width timing control (r77h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 m_bstp[1:0] 0 0 0 0 0 m_bpw[2:0] default 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 m_bstp: control the start timing of catching the red signal output. set up in the range b_stp < m_bstp 3 + b_stp. m_bstp[1:0] osc clock (1 mhz) dotclk (18/16-bit, 5mhz) 0 0 disable disable 0 1 1 clock cycle 1 clock cycle x 4 1 0 2 clock cycle 2 clock cycle x 4 1 1 3 clock cycle 3 clock cycle x 4 m_bpw: control the pulse width of catching the red signal output. m_bpw[2:0] osc clock (1 mhz) dotclk (18/16-bit, 5mhz) 0 0 0 8 clock cycle 8 clock cycle x 4 0 0 1 9 clock cycle 9 clock cycle x 4 0 1 0 10 clock cycle 10 clock cycle x 4 0 1 1 11 clock cycle 11 clock cycle x 4 1 0 0 12 clock cycle 12 clock cycle x 4 1 0 1 13 clock cycle 13 clock cycle x 4 1 1 0 14 clock cycle 14 clock cycle x 4 1 1 1 disable disable vcom output control (r78h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vmchg[1:0] default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vmchg: control the start timing of the vcom signal output. set up in the range 1 vmchg 4. vmchg[1:0] osc clock (1 mhz) dotclk (18/16-bit, 5mhz) 0 0 1 clock cycle 1 clock cycle x 4 0 1 2 clock cycle 2 clock cycle x 4 1 0 3 clock cycle 3 clock cycle x 4 1 1 4 clock cycle 4 clock cycle x 4 free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 164 panel signal control 1 (r79h): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 lgs p_o ff lgc lk4_ off lgc lk3_ off lgc lk2_ off lgc lk1_ off 0 rg sp_ off rg clk 4_o ff rg clk 3_o ff rgc lk2 _of f rgc lk1 _of f r_o ff g_o ff b_o ff default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lgsp_off: gsp output is controlled. ?0?: normal operation (default), ?1?: off lgclk4_off: gclk4 output is controlled. ?0?: normal operation (default), ?1?: off lgclk3_off: gclk3 output is controlled. ?0?: normal operation (default), ?1?: off lgclk2_off: gclk2 output is controlled. ?0?: normal operation (default), ?1?: off lgclk1_off: gclk1 output is controlled. ?0?: normal operation (default), ?1?: off rgsp_off: gsp output is controlled. ?0?: normal operation (default), ?1?: off rgclk4_off : gclk4 output is controlled. ?0?: normal operation (default), ?1?: off rgclk3_off : gclk3 output is controlled. ?0?: normal operation (default), ?1?: off rgclk2_off : gclk2 output is controlled. ?0?: normal operation (default), ?1?: off rgclk1_off : gclk1 output is controlled. ?0?: normal operation (default), ?1?: off r_off : rsw output is controlled. ?0?: normal operation (default), ?1?: off g_off : gsw output is controlled. ?0?: normal operation (default), ?1?: off b_off : bsw output is controlled. ?0?: normal operation (default), ?1?: off free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 165 panel signal control 2 (r7ah): r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 lgs p_p ol lgc lk4_ pol lgc lk3_ pol lgc lk2_ pol lgc lk1_ pol 0 rgs p_p ol rg clk 4_p ol rg clk 3_p ol rgc lk2 _po l rgc lk1 _po l r_p ol g_p ol b_p ol default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lgsp_pol : gsp polarity is controlled. ?0?: low active pulse generation, ?1?: high active pulse generation (default) lgclk4_pol : gclk4 polarity is controlled. ?0?: low active pulse generation (default), ?1?: high active pulse generation lgclk3_pol : gclk3 polarity is controlled. ?0?: low active pulse generation (default), ?1?: high active pulse generation lgclk2_pol : gclk2 polarity is controlled. ?0?: low active pulse generation (default), ?1?: high active pulse generation lgclk1_pol : gclk1 polarity is controlled. ?0?: low active pulse generation (default), ?1?: high active pulse generation rgsp_pol : gsp polarity is controlled. ?0?: low active pulse generation, ?1?: high active pulse generation (default) rgclk4_pol : gclk4 polarity is controlled. ?0: low active pulse generation (default), ?1?: high active pulse generation rgclk3_pol : gclk3 polarity is controlled. ?0: low active pulse generation (default), ?1?: high active pulse generation rgclk2_pol : gclk2 polarity is controlled. ?0: low active pulse generation (default) ,?1: high active pulse generation rgclk1_pol : gclk1 polarity is controlled. ?0: low active pulse generation (default), ?1: high active pulse generation r_pol : rsw polarity is controlled. ?0: low active pulse generation (default), ?1?: high active pulse generation g_pol : gsw polarity is controlled. ?0: low active pulse generation (default), ?1?: high active pulse generation b_pol : bsw polarity is controlled. ?0: low active pulse generation (default), ?1?: high active pulse generation free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 166 gate1 and gate2 switching control (r97h) r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0 0 0 0 0 0 chn g 0 0 0 0 0 0 0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chng: this register swap gclk1 signal & gclk2 signal. 0 : normal operation 1: swap operation free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 167 8. dc / ac characteristics 8.1 absolute maximum ratings table 8.1.1 absolute maximum rating (vss = 0 v) item symbol rating unit supply voltage vdd ? vss -0.3 ~ 3.0 v supply voltage 3 vdd3 ? vss -0.3 ~ 5.0 v supply voltage for step-up circuit vci ? vss -0.3 ~ 5.0 v avdd ? vss -0.3 ~ 6.5 v lcd supply voltage range |vgh ? vgl| -0.3 ~ 35 v input voltage range vin -0.3 to vdd3 +0.5 v operating temperature t opr -40 ~ 85 c storage temperature t stg -55 ~ 110 c notes: 1. absolute maximum rating is the limit value beyond which the ic may be broken. they do not assure operations. 2. operating temperature is the range of device-operating temperature. they do not guarantee chip performance. 3. absolute maximum rating is guaranteed when our company?s package used. free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 168 8.2 lcd driver dc characterisics table 8.2.1 dc characteristics (vss = 0 v) characteristic symbol condition min typ max unit note vdd 1.4 1.5 1.6 v *1 operating voltage vdd3 1.65 - 3.3 v *1 vgh 7.5 - 16.0 v vgl -11 - -5.5 v vglrout -10.5 - -5.0 v avdd 3.4 - 6.0 v lcd driving voltage gvdd 3. - 5.0 v input high voltage vih 0.8*vdd3 - vdd3 v *2 input low voltage vil 0 - 0.2*vdd3 v *2 output high voltage voh ioh = -0.5ma 0.7*vdd3 - vdd3 v *3 output low voltage vol iol = 0.5ma 0 - 0.3*vdd3 v *3 input leakage current iil vin = vss or vdd3 -1.0 1 ua *2 output leakage current iol vin = vss or vdd3 -3.0 3.0 ua *3 operating frequency fosc frame freq. = 70 hz display line = 320 1.0 mhz *4 external supply voltage vci 2.5 3.3 v 1 st step-up input voltage vci1 1.75 3.0 v 1 st step-up output efficiency avdd iload = 4 ma 90 95 100 % 2 nd step-up output efficiency vgh iload = 0.1 ma 90 95 100 % 3 rd step-up output efficiency vgl iload = 0.1 ma 90 95 100 % notes: 1. vss = 0v. 2. applied pins; im3-0, csb, e_rdb, rw_wrb, rs, db0 to db17, pd0 to pd17, pregb, resetb. 3. applied pins; db0 to db17 4. target frame frequency = 70 hz, display line = 320, back porch = 4, front porch = 4 internal rtn [4:0] register = ?0_1011? ( you can measure osc (fosc) or cl1 (fosc/43)) free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 169 table 8.2.2 dc characteristics for lcd driver outputs (vdd = 1.5 v, vdd3 = 3.0v, vss = 0v) characteristic symbol condition min typ max unit note lcd gate driver output on resistance ron 2.5 kohm lcd mux driver output on resistance ron vgh=16.0v, vgl=-11.0v vglrout = -10.5v 1.5 kohm sap = ?001? - - 8.5 us *1 sap = ?010? - - 7.5 us *1 sap = ?011? - - 6.5 us *1 sap = ?100? - - 6 us *1 sap = ?101? 5.5 us *1 sap = ?110? 5 us *1 lcd source driver delay tsd sap = ?111? 4.0 us *1 4.2v ?a v so - ??20 ??55 mv *2 0.8v 240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 170 8.3 cpu / rgb / serial interface ac characteristics 8.3.1 68-system 18-/16-/9-/8-bit interface figure 8.3.1.1 ac timing parameter and timing diagram of 68-system interface table 8.3.1.1 ac timing characteristics (vdd = 1.5 v, vdd3 = 1.65 to 3.3v, t a = -40 to +85 o c) parameter symbol condition min. max. unit address setup time tas68 5 - ns address hold time tah68 rs ~ csb rw_wrb ~ csb 5 - ns chip select setup time tcss68 5 - ns chip select holed time tcsh68 5 - ns chip select wait time tcsf68 csb ~ e_rdb 10 - ns write enable period tcycw68 65 - ns write enable high pulse width twhw68 22.5 - ns write enable low pulse width twlw68 e_rdb when rw_wrb = 0 22.5 - ns read enable period tcycr68 400 - ns read enable high pulse width twhr68 190 - ns read enable low pulse width twlr68 e_rdb when rw_wrb = 1 190 - ns write data setup time twds68 10 - ns write data hold time twdh68 db ~ e_rdb 10 - ns read data delay time trdd68 - 160 ns read data hold time trdh68 db ~ e_rdb 5 40 ns rising time tr - 10 ns falling time tf all signals - 10 ns free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 171 8.3.2 80-system 18-/16-/9-/8-bit interface figure 8.3.2.1 ac timing parameter and timing diagram of 80-system interface table 8.3.2.1 ac timing characteristics (vdd = 1.5 v, vdd3 = 1.65 to 3.3v, t a = -40 to +85 o c) parameter symbol condition min. max. unit address setup time tas80 5 - ns address hold time tah80 rs ~ csb 5 - ns chip select setup time tcss80 5 - ns chip select holed time tcsh80 5 - ns chip select wait time tcsf80 csb ~ rw_wrb csb ~ e_rdb 10 - ns write enable period tcycw80 65 - ns write enable low pulse width twlw80 22.5 - ns write enable high pulse width twhw80 rw_wrb 22.5 - ns read enable period tcycr80 400 - ns read enable low pulse width twlr80 190 - ns read enable high pulse width twhr80 e_rdb 190 - ns write data setup time twds80 5 - ns write data hold time twdh80 db ~ rw_wrb 5 - ns read data delay time trdd80 10 - ns read data hold time trdh80 db ~ e_rdb 10 - ns rising time tr - 160 ns falling time tf all signals 5 40 ns free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 172 8.4 serial peripheral interface figure 8.4.1 ac timing parameter and timing diagram of serial peripheral interface table 8.4.1 ac timing characteristics (vdd = 1.5 v, vdd3 = 1.65 to 3.3v, t a = -40 to +85 o c) specification characteristic symbol min. max. unit write tscycw 130 - ns serial clock cycle time read tscycr 250 serial clock rise / fall time tr, tf - 10 ns write tschw 55 - ns pulse width high read tschr 115 - ns write tsclw 55 - ns pulse width low read tsclr 115 - ns chip select setup time tcss 20 - ns chip select hold time tcsh 60 - ns serial input data setup time tsids 30 - ns serial input data hold time tsidh 30 - ns serial output data delay time tsodd - 130 ns serial output data hold time tsodh 5 - ns free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 173 8.5 rgb interface figure 8.5.1 ac timing parameter and timing diagram of rgb interface table 8.5.1 ac timing characteristics (vdd = 1.5 v, vdd3 = 1.65 to 3.3v, t a = -40 to +85 o c) normal mode 18/16bit rgb interface 6bit rgb interface characteristic symbol min. max. min. max. unit dotclk cycle time tdcyc 100 - 55 - ns dotclk rise / fall time tr, tf - 10 10 ns dotclk pulse width high tdchw 40 - 17.5 - ns dotclk pulse width low tdclw 40 - 17.5 - ns vsync/hsync setup time tsyncs 15 - 15 - ns enable setup time tens 15 - 15 - ns enable hold time tenh 7 - 7 - ns db data setup time tdbs 15 - 15 - ns db data hold time tdbh 7 - 7 - ns free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 174 8.6 reset timing tres resetb vil vil figure 8.6.1 ac timing parameter and timing diagram of reset table 8.6.1 ac characteristics of reset (vdd = 1.5 v, vdd3 = 1.65 to 3.3v, t a = -40 to +85 o c) characteristic symbol min. max. unit reset low pulse width tres 15 - us free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 175 8.7 mddi io dc / ac characteristics table 8.7.1 data / strobe rx dc characteristics parameter description min typ max unit note v it+ receiver differential input high threshold voltage. above this differential voltage the input signal shall be interpreted as a logic one level. 50 mv v it- receiver differential input low threshold voltage. below this differential voltage the input signal shall be interpreted as a logic zero level. -50 mv v it+ receiver differential input high threshold voltage (offset for hibernation wake-up). above this differential voltage the input signal shall be interpreted as a logic-one level. 125 175 mv v it- receiver differential input low threshold voltage (offset for hibernation wake-up). below this differential voltage the input signal shall be interpreted as logic zero level. 75 125 mv v input-range allowable receiver input voltage range with respect to client ground. 0 1.65 v r term parallel termination resistance value 98 100 102 ? table 8.7.2 data/strobe rx ac characteristics parameter description min typ max unit note v it+ receiver differential input high threshold voltage in ac condition. 100 mv v it- receiver differential input low threshold voltage in ac condition. -100 mv table 8.7.3 driver electrical dc characteristics parameter description min typ max unit note i diffabs absolute driver differential output current range (current through the termination resistor) 2.5 4.5 ma r term = 100 ? v out-rng-int single-ended driver output voltage range with respect to ground, internal mode 0.35 1.60 v under all conditions, including double-drive note: please refer to vesa specification ver 1.0 free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 176 figure 8.7.1 mddi receiver, driver electrical diagram figure 8.7.2 host enable / disable time and client enable / disable time diagram notes: 1. tbit= 1 / link_data_rate, where link_data_rate is the bit rate of a single data pair (for example, if the average forward link bit rate is 200mbps, then tbit= 1 / 200mbps = 5ns) 2. these specifications are from vesa specification ver 1.0. free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 177 8.8 sub panel signal characteristics sub panel timing is described below. if 9/8 bit mode is used, each characteristics of sub panel timing is increased by 2 times, and register writing packet and memory writing packet have some differences. table 8.8.1 sub panel signal characteristics (k = mddi speed (mbps), 18bit 80 mode) specification (register) specification (memory) characteristic symbol min. max. min. max. unit cycle time tcycw80 10*(2000/k) - 8*(2000/k) - pulse rise / fall time **tr, tf - 8 - 8 pulse width low twlw80 4*(2000/k) - 8 - 4*(2000/k) - 8 - pulse width high twhw80 6*(2000/k)-8 - 4*(2000/k) - 8 - rw, rs and csb setup time tas80 3*(2000/k) - 3*(2000/k) - rw, rs and csb hold time tah80 3*(2000/k) - 3*(2000/k) - write data setup time twds80 5*(2000/k) - 5*(2000/k) - write data hold time twdh80 3*(2000/k) - 3*(2000/k) - ns figure 8.8.1 sub panel signal timing(80 mode) note : rl 200 ? (cl 3pf) pregb = low vdd3 = 1.8 ~ 3.3v ta = -40 ~ 85 ? free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 178 table 8.8.2 sub panel signal characteristics (k = mddi speed (mbps), 18bit 68 mode) specification (register) specification (memory) characteristic symbol min. max. min. max. unit cycle time tcycw68 10*(2000/k) - 8*(2000/k) - pulse rise / fall time **tr, tf - 8 - 8 pulse width low twlw68 6*(2000/k) - 8 - 4*(2000/k) - 8 - pulse width high twhw68 4*(2000/k)-8 - 4*(2000/k) - 8 - rw, rs and csb setup time tas68 3*(2000/k) - 3*(2000/k) - rw, rs and csb hold time tah68 3*(2000/k) - 3*(2000/k) - write data setup time twds68 5*(2000/k) - 5*(2000/k) - write data hold time twdh68 3*(2000/k) - 3*(2000/k) - ns figure 8.8.2 sub panel signal timing(68 mode) note : rl 200 ? (cl 3pf) pregb = low vdd3 = 1.8 ~ 3.3v ta = -40 ~ 85 ? free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 179 8.9 mtp dc / ac characteristics figure 8.9.1 voltages and waveform for mtp programming table 8.9.1 mtp writing time timing min max unit tvs 1 - ms tvh 1 - ms tdws 10 - us tdwh 10 - us tpgm 100 200 ms table 8.9.2 mtp_ep / mtp_pp voltage tolerance item pgm min typ max unit erase 21.0 21.5 22.0 tolerance of mtp_ep write 0 v erase 0 tolerance of mtp_pp write 17.0 17.5 18.0 v table 8.9.3 current consumption during setting mtp item symbol condition min typ max unit imtp_ep mtp_ep = 21.5v - - 0.6 current consumption during setting mtp imtp_pp mtp_pp = 17.5v - - 0.6 ma note: simulation result, with common power condition vdd3=2.8v, vdd=1.5v, vci=2.8v free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 180 9. applications 9.1 appication circuit example free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 181 revision history date contents version aug. 30, 2006 - preliminary version 0.0 ver. 0.0 sep. 27. 2006 - update the power right and ltps timing ver. 0.1 oct. 11, 2006 - update the external power on/off sequence and ltps timing ver. 0.2 oct. 30, 2006 - added vsync i/f, update ltps timing (r/g/b multiplexer) ver. 0.3 nov. 24. 2006 - removed vcl c31m, c31p, - pin name was changed(mtpd, mtpg, rw_wrb, e_rdb) - updated the ivdd3,ivci on stb and slp mode - mddi io dc / ac characteristics - table 5.2.1.1 display operation mode - 5.2.11.4 mtp sequence flow - power control 6 (r15h) (changed vcomh , vcomprec) - added vcom_off reg - table 7.2.9 function configuration table of direct vcom driving and coupling vcom driving method - display control 2 (r08h): back porch ? front porch - initial value of r7ah - serial interface timing diagram - removed 2 line interlace partial mode timing diagram - added 97h register - removed fuse align key - changed instruction setup flow - changed and added power od/of sequence - removed auto_c reg(r16h) ver. 0.31 dec. 18. 2006 - ltps timing value of register changed.(r72h ~ r77h) - vml(4:0) ? vml(5:0) : amplitude of voltage changed - (r16h) vcomh voltage changed - removed amp_ab register (r16h) - initial value of r16h changed - confirmed pad configuration - updated align key configuration - update pad center coordinates - dc & ac characteristics changed (iload, lcd source driver delay, gate, mux) - reset timing was updated - step_3 reg. was hidden - update application citcuit example - update cpu / rgb / serial interface ac characteristics - confirmed align key configuration and coordinate ver. 0.32 dec. 20. 2006 - update output voltages range - update power supply pins description - update output voltage amplitude of gate driver control pins and rgb switch control pins - update power circuit architecture - modified relation between r15h and mtp - removed 8.7ltps gate signal level shifter ac characteristics description - added 8.8 sub panel signal characteristics - removed pt = ?00? function on using the panel with gate driver. ver. 0.33 dec. 28. 2006 - changed size of input and output bump ver. 0.34 jan. 08. 2007 - changed eor function - correcting typo. - replaced vcomr register by vcmr register. ver. 0.35 jan. 11. 20067 - 5.2.4 rgb interface updated - chanhed ac timing (twds, twdh, trdd, ttdh) jan. 12. 2007 - the name of odd and even frame changed to 1st, 2nd frame in lcd driving waveform control ver. 0.36 free datasheet http:///
240 rgb source & 320 ltps with gram for 262k colors tft-lcd S6D1121 ver. 1.00 182 jan.25. 2007 - removed bt and changed gvd ? vrh in set up flow of power supply, - vgl ? vglrout in 126 pages - fmp2-0 ? fmp1-0 in 128 pages - vglrout values was changed in power control 4 (r13h) mar. 07. 2007 - vcomh = 2.65 x vcomr in power control 6 (r15h): - when r_stp[2:0] = 000 , r source output start point (r72h) was changed. (4 clocks ? 1 clocks) - when g_stp[2:0] = 111, , r source output start point (r73h) was changed.(disable ? 15clock cycles ) - when b_bpw[2:0] = 111, b mux start pulse width timing cont a (r77h) was changed (15 clock cycles ? disable) - the setup range of vmchg range was changed .(0 vmchg 3 ? 1 vmchg 4) - vcomr range was added - the function of vci1_off register was changed. and the circuit was added. - fld function was added on display control 1 (r07h) - rgb interface timing (vsync falling , hsync falling) - ivdd3 current consumption during normal operation was changed from 150 ua to 200ua. - shorted contacts to vss. - the set up flows of power supply were changed. - the vr1c register initial value was changed . - figure 5.5.4.1 memory data read sequence was changed. - figure 5.5.4.2 memory data write sequence was changed. - added window display sequence diagram. ver. 0.37 mar. 09. 2007 - added pad size discription and in-chip height description. - removed vglrout in table 8.2.1 dc characteristics - changed min & max value of v so - modified description of vma in r15h ver. 0.38 apr. 20. 2007 - in rgb and vsync mode, bp + fp must be even value. - added vgh and vgl cap. information. ver. 0.39 may. 15. 2007 - avdd minium voltage changed (4.02 ? 3.4) - corrected errors. - corrected top block diagram . - modified power sequence diagram. - coupling mode power sequence change - vc register table change - added temperature condition in lcd source driver output voltage range ver 0.40 may. 26. 2007 - S6D1121 spec 1.00 version release. ver 1.00 free datasheet http:///
S6D1121 ver. 1.00 240 rgb source & 320 ltps with gram for 262k colors tft-lcd 183 notice precautions for light when S6D1121 is exposed to light, it may cause motion of electrons inside the semiconductors, which might lead to a change in device characteristics. hence, the users of the packages who may expose chips to external light such as cob, cog, tcp and cof must consider effective methods to block out light from reaching the ic on all parts of the surface area, the top, bottom and the sides of the chip. follow the precautions below when using the products. consider and verify the penetrating light protection to the ic at substrate (board or glass) or product design stage. always test and inspect products under the environment with no penetration of light free datasheet http:///

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